Stacked Image Sensor Array Segmentation for Faster Pixel Control

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Solution Overview

Problem

In solid state image sensors, the long lengths of pixel control lines due to their arrangement in a row direction lead to significant delays caused by line resistances and parasitic capacitances, hindering the speeding up of pixel control, especially when penetration vias are located at the end of the pixel array unit.

Innovation Solution

The pixel array unit is divided into multiple sections, reducing the length of pixel control lines, and electrical connections are established through electrodes on the substrate surfaces between the pixel array unit and the control circuit unit, eliminating the need for penetration vias and reducing time constants.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Stability of the object's composition

If pixel control lines are arranged to traverse the pixel array unit in the row direction, then the pixel array unit can be controlled uniformly, but the line lengths become long and the time constants become large, decreasing the signal transmission speed

Engineering Contradiction:
Improveuniform control of pixel array unitVSAvoidsignal transmission speed
Core Design Contradiction:
Stability of the object's compositionVSSpeed

Solution Approach 1:

The pixel array unit is divided into multiple divided array units, and the pixel control lines are segmented to traverse each divided array unit individually. This segmentation reduces the length of each control line segment, thereby reducing the time constants and improving signal transmission speed while maintaining uniform control through coordinated operation of multiple control lines across the divided units.

Inventive Principle:
Principle #1Segmentation

2Device complexity

If penetration vias are located at the end portion of the pixel array unit, then the pixel array unit structure is simplified, but the pixel control lines must be long to reach the end portion, causing large delays due to line resistances and parasitic capacitances

Engineering Contradiction:
Improvepixel array unit structureVSAvoidcontrol signal delay
Core Design Contradiction:
Device complexityVSLoss of time

Solution Approach 1:

The penetration vias are moved from the end portion of the pixel array unit to the intermediate region, utilizing the two-dimensional space more effectively. This dimensional repositioning allows control lines to connect to vias at multiple points along the array, reducing the maximum line length and the associated time delays while maintaining structural simplicity.

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

3Device complexity

If the pixel array unit is not divided, then the control circuit unit can be positioned at one location, but the control lines must traverse the entire array, resulting in large time constants and slow pixel control

Engineering Contradiction:
Improvecontrol circuit unit positioningVSAvoidpixel control speed
Core Design Contradiction:
Device complexityVSProductivity

Solution Approach 1:

The pixel array unit is divided into multiple divided array units, each with its own control lines connecting to penetration vias in the control circuit unit. This segmentation reduces control line lengths and time constants, improving pixel control speed. The control circuit unit remains positioned at one location (the intermediate region), maintaining structural simplicity while enabling faster control through the segmented architecture.

Inventive Principle:
Principle #1Segmentation

Data Source

PatentUS11889218B2Stacked substrate solid state image sensor
Publication Date: 2024.01.30 SONY GROUP CORP
  • US11889218B2 patent drawing
  • US11889218B2 patent drawing
  • US11889218B2 patent drawing

AI summary

A solid state image sensor of the present disclosure includes: a first semiconductor substrate provided with at least a pixel array unit in which pixels that perform photoelectric conversion are arranged in a matrix form; and a second semiconductor substrate provided with at least a control circuit unit that drives the pixels. The first semiconductor substrate and the second semiconductor substrate are stacked, with first surfaces on which wiring layers are formed facing each other, the pixel array unit is composed of a plurality of divided array units, the control circuit unit is provided corresponding to each of the plurality of divided array units, and electrical connection is established in each of the divided array units, through an electrode located on each of the first surfaces of the first semiconductor substrate and the second semiconductor substrate, between the pixel array unit and the control circuit unit.