Stacked Image Sensor Pixel Cell Vertical Transfer Transistor
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Solution Overview
Problem
Miniaturization of CMOS image sensors has led to a loss of pixel photosensitivity and dynamic range, necessitating new approaches to improve stacked image sensor design, particularly in reducing pixel array size and manufacturing costs.
Innovation Solution
The implementation of a pixel cell with a photodiode on a first semiconductor chip and a readout circuit on a second chip, coupled by a vertical channel transfer transistor, allows for efficient transfer of image charge and reduces the size and cost of the pixel array by separating the photodiode and circuitry across stacked chips.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If photodiode and readout circuit are integrated on the same chip, then device complexity is reduced, but pixel array size increases and photosensitivity decreases
Solution Approach 1:
The image sensor is divided into two separate chips: a first chip containing the photodiode array for light sensing, and a second chip containing the readout circuitry. This segmentation allows each chip to be optimized independently, reducing the pixel array size on the sensor chip while maintaining overall device functionality.
Solution Approach 2:
The patent transitions from a planar integration approach to a three-dimensional stacked architecture. By stacking the readout circuit chip over the photodiode chip and using vertical interconnects, the design utilizes the third dimension (height/stacking direction) to reduce the lateral footprint of the pixel array.
2Ease of manufacture
If photodiode and readout circuit are integrated on the same chip, then manufacturing process is simplified, but photosensitivity and dynamic range decrease
Solution Approach 1:
Separating the photodiode array and readout circuit into different chips allows each component to be manufactured using optimized processes tailored to its specific requirements, potentially improving photosensitivity through specialized fabrication techniques for the photodiode chip.
Solution Approach 2:
The patent introduces a vertical channel transfer transistor as an intermediary component between the photodiode chip and readout circuit chip. This transfer transistor efficiently moves photocharges across the chip interface, maintaining signal integrity and photosensitivity despite the physical separation of components.
3Productivity
If vertical channel transfer transistor is added, then image charge transfer efficiency improves, but device complexity increases
Solution Approach 1:
The vertical channel transfer transistor serves as an intermediary element that facilitates efficient charge transfer between the photodiode array on the first chip and the readout circuit on the second chip. This specialized transfer mechanism improves charge transfer efficiency while the stacked architecture keeps the overall device footprint compact.
Solution Approach 2:
The transfer transistor is configured with a vertical channel orientation, utilizing the vertical stacking direction rather than lateral space. This dimensional reorientation allows for efficient charge transfer without significantly increasing the lateral device footprint.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration enhances image sensor performance by reducing pixel array size and manufacturing costs while maintaining or improving photosensitivity and dynamic range, addressing the limitations of prior art in stacked image sensor design.
Implementation Method 1
The photodiode is disposed within a first substrate of a first semiconductor chip for accumulating an image charge in response to light incident upon the photodiode
Data Source
AI summary
A pixel cell has a photodiode, a readout circuit, and a vertical transfer transistor. The photodiode is disposed within a first substrate of a first semiconductor chip for accumulating an image charge in response to light incident upon the photodiode. The readout circuit is disposed within a second substrate of a second semiconductor chip. The vertical transfer transistor is coupled between the photodiode and the readout circuitry to transfer the image charge from the photodiode to the readout circuitry.