Stacked Imaging Element Layout for Smaller Pixel Readout Circuits
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
The existing solid-state imaging devices have a complex structure for connecting readout signals to the signal scanning circuit, leading to difficulties in miniaturization due to the large number of transistors in the semiconductor substrate.
Innovation Solution
The imaging element is designed with a simplified configuration, featuring at least a photoelectric conversion section, a first transistor, and a second transistor, where the photoelectric conversion layer extends with specific electrode configurations, allowing for a reduced transistor area and simplified interconnections, thereby improving charge-to-voltage conversion efficiency and signal-to-noise ratio.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If a conventional solid-state imaging device structure is used with multiple transistors in the semiconductor substrate, then the readout signal connection is established, but the device complexity increases and miniaturization becomes difficult
Solution Approach 1:
The patent moves transistors from the semiconductor substrate plane to the surface of the imaging element, utilizing the vertical dimension. This spatial reorganization reduces in-plane transistor area and simplifies the substrate structure while maintaining electrical connectivity through vertical interconnections.
Solution Approach 2:
The imaging element is divided into functionally independent modules: photoelectric conversion section, transistor section, and signal processing section. Each module is optimized separately, with the transistor section containing reset, amplification, and selection transistors that can be independently designed and connected to the readout circuit.
2Measurement precision
If the photoelectric conversion layer is extended with additional sections, then the charge-to-voltage conversion efficiency is improved, but the manufacturing complexity increases
Solution Approach 1:
The photoelectric conversion layer extension section serves multiple functions: it extends the photoelectric conversion area to improve charge generation, acts as a charge accumulation region, and provides a platform for integrating transistor components. This multi-functionality improves conversion efficiency without proportionally increasing manufacturing complexity.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration simplifies the imaging element structure, reduces its area, enhances resolution, and improves charge-to-voltage conversion efficiency and signal-to-noise ratio, facilitating miniaturization and better image quality.
Implementation Method 1
a photoelectric conversion layer that has a first surface and a second surface opposed to the first surface and on which light is incident from a first surface side
Data Source
AI summary
An imaging element has at least a photoelectric conversion section, a first transistor TR1, and a second transistor TR2, the photoelectric conversion section includes a photoelectric conversion layer 13, a first electrode 11, and a second electrode 12, the imaging element further has a first photoelectric conversion layer extension section 13A, a third electrode 51, and a fourth electrode 51C, the first transistor TR1 includes the second electrode 12 that functions as one source/drain section, the third electrode that functions as a gate section 51, and the first photoelectric conversion layer extension section 13A that functions as the other source/drain section, and the first transistor TR1 (TRrst) is provided adjacent to the photoelectric conversion section.