Stacked Imaging Device Pixel Architecture for Sensitivity Resolution Trade-off
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Solution Overview
Problem
Miniaturization of imaging device pixels has led to insufficient sensitivity and dynamic range due to reduced photodiode area, necessitating an enhancement in imaging device performance for high-resolution and high-sensitivity applications.
Innovation Solution
The imaging device incorporates a pixel circuit with a photoelectric conversion device and multiple transistors formed on two semiconductor substrates, where the transistors on one substrate overlap with the photoelectric conversion device, increasing the area occupied by the photodiode and improving sensitivity and resolution.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If the pixel size is miniaturized to increase resolution, then the imaging device achieves high resolution, but the photodiode area is reduced causing insufficient sensitivity
Solution Approach 1:
The patent applies three-dimensional stacking architecture where the photoelectric conversion device is formed on a first semiconductor substrate and transistor circuits are formed on a second semiconductor substrate positioned above it. This vertical arrangement allows the photodiode area to be maximized in the horizontal plane while transistor circuits occupy the vertical space, effectively resolving the contradiction between pixel miniaturization for high resolution and maintaining sufficient photodiode area for high sensitivity.
Solution Approach 2:
The pixel circuit is segmented into two separate semiconductor substrates: the first substrate contains the photoelectric conversion device while the second substrate contains the transistor circuits. This segmentation allows independent optimization of each component - the photodiode can be maximized in area on the first substrate while transistors are compactly arranged on the second substrate, thereby maintaining both high resolution and high sensitivity.
2Reliability
If the photodiode area is increased to improve sensitivity, then the imaging device achieves high sensitivity, but the pixel size increases reducing resolution
Solution Approach 1:
By transitioning from a planar two-dimensional layout to a three-dimensional stacked architecture, the patent enables the photodiode to occupy maximum area within the pixel's horizontal footprint while transistor circuits are positioned in the vertical dimension above the first substrate. This allows large photodiode area for high sensitivity without increasing the horizontal pixel dimensions, thereby maintaining high resolution.
3Adaptability or versatility
If more transistor circuits are integrated in each pixel to improve functionality, then the imaging device achieves high performance, but the area occupied by non-photodiode elements increases reducing the photodiode area
Solution Approach 1:
The patent relocates transistor circuits from the same plane as the photodiode to a separate second semiconductor substrate positioned vertically above the first substrate. This vertical separation allows multiple transistor circuits to be integrated in each pixel without consuming horizontal photodiode area, thereby maintaining both high functionality and large photodiode area for high sensitivity.
Solution Approach 2:
By segmenting the pixel circuit into two spatially separated components on different substrates, the patent allows the photodiode to occupy maximum area on the first substrate while transistor circuits are compactly integrated on the second substrate. This segmentation enables high functionality with multiple transistors per pixel without compromising photodiode area.
4Area of stationary object
If the pixel circuit is shared by multiple pixels to reduce element area, then the area occupied by non-photodiode elements is reduced, but the complexity of the circuit increases
Solution Approach 1:
The patent utilizes the vertical dimension by forming transistor circuits on a second semiconductor substrate above the first substrate containing the photodiode. This three-dimensional arrangement allows efficient sharing of transistor circuits among multiple pixels while maintaining clear spatial separation and organized interconnections, thereby reducing non-photodiode element area without excessively increasing circuit complexity.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration allows for an imaging device with enhanced sensitivity and resolution, capable of high-speed operation while maintaining a compact size, addressing the limitations of miniaturized pixel sizes.
Implementation Method 1
The first semiconductor substrate includes a photoelectric conversion device
Data Source
AI summary
An imaging device includes a first semiconductor substrate and a second semiconductor substrate. The first semiconductor substrate includes a photoelectric conversion device and a first transistor. The second semiconductor substrate includes a second transistor, a third transistor, and a fourth transistor. One electrode of the photoelectric conversion device is electrically connected to one of a source and a drain of the first transistor. The other of the source and the drain of the first transistor is electrically connected to one of a source and a drain of the second transistor and a gate of the third transistor. One of a source and a drain of the third transistor is electrically connected to one of a source and a drain of the fourth transistor. The photoelectric conversion device and at least parts of the second transistor, the third transistor, and the fourth transistor overlap with each other.