Stacked Imaging Pixel Circuits for On-Sensor Product-Sum Processing
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Imaging devices require advanced functions, high-speed operation, low power consumption, and efficient image processing capabilities while maintaining a compact size, which existing technologies struggle to achieve.
Innovation Solution
An imaging device with stacked pixel blocks and circuits, including pixel circuits, memory circuits, product-sum operation circuits, and binarization circuits, utilizing transistors with metal oxide in the channel formation region, and incorporating memory cells with ferroelectric layers for efficient image processing.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If image processing functions are added to the imaging device, then the device's functionality and intelligence are improved, but the circuit area and device size increase
Solution Approach 1:
The patent implements a stacked configuration where pixel circuits are arranged in a first layer and image processing circuits are arranged in a second layer above the first layer. This three-dimensional stacking approach allows multiple functional circuits to coexist in a compact space, enabling image processing capabilities without significantly increasing the planar circuit area.
2Area of stationary object
If multiple circuits are stacked to reduce area, then the device size is reduced, but the wiring complexity and manufacturing difficulty increase
Solution Approach 1:
The imaging device is segmented into distinct functional layers: a first layer containing pixel circuits and a second layer containing image processing circuits. This segmentation allows each layer to be optimized independently for its specific function while reducing inter-layer wiring complexity through localized connections between adjacent circuits in different layers.
3Device complexity
If processing is performed externally, then the imaging device structure remains simple, but communication speed decreases and peripheral device load increases
Solution Approach 1:
The patent merges the pixel circuits in the first layer with image processing circuits in the second layer to form an integrated imaging device. This combination enables on-device image processing, eliminating the need for external communication and processing, thereby improving communication speed and reducing peripheral device load while maintaining a unified device structure.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
Enables high-speed, low-power image processing with reduced circuit area and wiring length, enhancing the device's reliability and functionality.
Implementation Method 1
memory cells each including a transistor and a capacitor including a ferroelectric layer
Data Source
AI summary
An imaging device that has an image processing function and is capable of operating at high speed is provided. The imaging device has an additional function such as image processing, image data obtained by an imaging operation is binarized in a pixel portion, and a product-sum operation is performed using the binarized data. A memory circuit is provided in the pixel portion and retains a weight coefficient used for the product-sum operation. Thus, an arithmetic operation can be performed without the weight coefficient read from the outside every time, so that power consumption can be reduced. Furthermore, a pixel circuit, a memory circuit, and the like and a product-sum operation circuit and the like are formed to be stacked; therefore, the length of a wiring between the circuits can be shortened, and a low-power consumption operation and a high-speed operation can be performed.