Stacked Power-Ground Interconnect Layout for Denser Signal Routing
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Solution Overview
Problem
The limited space available for signal lines in silicon-based devices due to the presence of power and ground lines in the same horizontal plane restricts the density and efficiency of interconnect structures.
Innovation Solution
The implementation of vertically stacked power and ground lines within dielectric layers, allowing additional signal tracks within the same footprint by isolating these lines electrically and positioning them vertically, thereby optimizing the use of chip area.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of moving object
If power and ground lines are arranged in the same horizontal plane, then electrical connection is simplified, but available space for signal lines is reduced
Solution Approach 1:
The patent transitions from a two-dimensional horizontal arrangement of power and ground lines to a three-dimensional vertical stacked configuration. Power lines and ground lines are positioned in different metallization layers vertically, allowing signal lines to be routed in the horizontal plane without spatial conflict. This dimensional change resolves the contradiction by providing both adequate space for signal lines and maintained electrical connection simplicity through vertical stacking.
Solution Approach 2:
The interconnect structure is segmented into multiple metallization layers, with power lines and ground lines separated into different vertical levels. This segmentation allows independent optimization of power/ground routing and signal routing in the horizontal plane, increasing available space for signals while maintaining electrical connection functionality through the layered architecture.
2Productivity
If more signal lines are added to increase density, then routing efficiency improves, but available chip area is reduced
Solution Approach 1:
By moving power and ground lines to the vertical dimension through stacked metallization layers, the horizontal chip area is freed up for additional signal lines. This allows increased routing density and higher productivity without expanding the physical chip footprint, as the power/ground infrastructure occupies the vertical space rather than competing for horizontal real estate.
Solution Approach 2:
The structure implements a nested arrangement where power lines and ground lines are embedded in different vertical layers, with signal lines nested in the horizontal plane. This nesting allows multiple interconnect functions to coexist in a compact volume, enabling higher routing efficiency within the same chip area by utilizing three-dimensional space allocation.
3Area of stationary object
If vertically stacked power and ground lines are implemented, then chip area is reduced, but manufacturing complexity increases
Solution Approach 1:
The vertical stacking of power and ground lines in different metallization layers reduces chip area by utilizing the third dimension. While this adds manufacturing steps for multi-layer deposition and patterning, standard semiconductor fabrication processes are employed to manage the complexity, making the approach feasible for industrial production.
Solution Approach 2:
The interconnect structure is built using sequential deposition and patterning of metallization layers, where each layer is prepared and connected in advance before final assembly. This preliminary action approach, following standard backend-of-line processing flows, manages fabrication complexity by breaking down the complex vertical stacking into manageable sequential steps that can be executed with existing manufacturing capabilities.
Data Source
AI summary
Interconnect structures including signal lines, power lines and ground lines are configured for improvements in routing and scaling. Vertical stacking of the relatively wide power and ground lines allows for additional signal tracks in the same footprint of a standard cell or other electronic device. Alternatively, vertical stacking of the signal lines allows an increased number of signal tracks. Such interconnect structures are formed during back-end-of-line processing using subtractive or damascene interconnect integration techniques.