Stacked Interconnect Assembly for Thermal-Cycle-Resistant Solder Joints
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Solution Overview
Problem
Conventional wafer-level packaging processes face issues with small solder joints failing due to thermal cycling and require complex alignment processes, which can damage the solder balls and increase production costs.
Innovation Solution
A method involving the formation of first interconnect elements on a semiconductor workpiece, followed by a protective layer deposition that exposes portions of these elements, and subsequent reshaping to facilitate precise alignment and attachment of second interconnect elements, forming robust connections without material removal or complex alignment marks.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional wafer-level packaging uses single solder balls, then the manufacturing process is simple, but the structural integrity of solder joints is insufficient under thermal cycling
Solution Approach 1:
The patent implements stacked interconnect elements where multiple interconnect structures are vertically nested one above another, forming a columnar arrangement. This nesting approach increases the length of the solder joint path without expanding the lateral footprint, thereby enhancing structural integrity under thermal cycling while maintaining a compact form factor suitable for wafer-level packaging.
Solution Approach 2:
The invention transitions from a planar single-layer interconnect structure to a three-dimensional stacked structure by adding the vertical dimension. Multiple interconnect elements are arranged in columns extending through the substrate thickness, converting a two-dimensional bond pad arrangement into a three-dimensional interconnect architecture that provides redundant load paths and improved thermal-mechanical reliability.
2Manufacturing precision
If alignment marks are formed on the workpiece for accurate solder ball alignment, then alignment precision improves, but the workpiece surface area is reduced and tooling complexity increases
Solution Approach 1:
The patent uses alignment marks that are formed as copies or references on the workpiece surface, which are then used to guide the placement of subsequent interconnect elements. These alignment marks serve as template references that enable precise positioning without requiring additional complex tooling systems, as the marks themselves provide the positional information needed for accurate alignment.
Solution Approach 2:
The invention replaces complex mechanical alignment tooling with a marking and detection system. Instead of using elaborate mechanical fixtures or jigs to ensure alignment, the patent forms alignment marks on the workpiece that can be detected by imaging or sensing systems, substituting mechanical alignment methods with optical or electronic detection methods that require minimal physical intervention.
3Strength
If multiple stacked interconnect elements are formed, then joint length increases and strain energy decreases, but the manufacturing process becomes more complex
Solution Approach 1:
The patent forms alignment marks and preliminary structural features on the workpiece before depositing and patterning the stacked interconnect elements. This preliminary action establishes a reference framework that guides subsequent manufacturing steps, ensuring that multiple interconnect layers can be formed with consistent alignment and positioning without requiring complex real-time adjustment mechanisms during the deposition process.
Solution Approach 2:
The invention segments the interconnect structure into multiple discrete stacked elements or layers, each of which can be formed, patterned, and aligned independently. This segmentation allows for modular manufacturing where each interconnect layer can be processed separately and then assembled into the final stacked configuration, simplifying the overall manufacturing complexity compared to forming a monolithic multi-layer structure in a single step.
Data Source
AI summary
Microelectronic devices and method of forming a plurality of microelectronic devices on a semiconductor workpiece are disclosed herein. One such method includes placing a plurality of first interconnect elements on a side of a semiconductor workpiece, forming a layer on the side of the workpiece, reshaping the first interconnect elements by heating the first interconnect elements, and coupling a first portion of a plurality of individual second interconnect elements to corresponding first interconnect elements with a second portion of the individual second interconnect elements exposed.