Stacked Interposer Package via Conductive Vias
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Solution Overview
Problem
Existing semiconductor package designs fail to maximize space efficiency on printed circuit boards due to limitations in form factor and mounting density, particularly when stacking multiple packages or devices.
Innovation Solution
A semiconductor package configuration featuring two complimentary laminate substrate elements, where the bottom substrate is populated with electronic components, encapsulated, and drilled with vias filled with conductive metal for top substrate interposer connection, enabling 'lands-over-top' routing and embedding of multiple components.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of stationary object
If conventional semiconductor package designs are used, then manufacturing and assembly are straightforward, but space efficiency on printed circuit boards is not maximized due to limitations in form factor and mounting density
Solution Approach 1:
The patent transitions from conventional planar package mounting to a three-dimensional stacked configuration. Multiple semiconductor packages are vertically stacked and interconnected through conductive vias that penetrate through the package bodies, enabling space-efficient vertical integration while maintaining electrical connectivity between layers. This dimensional change from 2D to 3D packaging directly addresses the space efficiency requirement.
Solution Approach 2:
The patent implements a nested structure where multiple semiconductor packages are positioned one within another in a vertical stack. Each package contains semiconductor dies, leadframes, and encapsulant materials, and these packages are nested together with interconnection structures penetrating through them. This nesting approach maximizes the use of vertical space on the printed circuit board while maintaining functional integrity of each individual package.
2Productivity
If multiple semiconductor packages are stacked to maximize mounting density, then space utilization improves, but form factor requirements and electrical interconnection complexity increase
Solution Approach 1:
The patent introduces conductive vias as intermediary structures that facilitate electrical connections between stacked semiconductor packages. These vias penetrate through the encapsulant materials and leadframe structures, providing direct conductive pathways between corresponding electrical contacts on different package layers. This intermediary approach simplifies the interconnection process compared to traditional wire bonding or PCB trace routing between stacked packages.
Solution Approach 2:
The patent divides the electrical interconnection system into discrete segments corresponding to each stacked package layer. Each package maintains its own internal leadframe and contact structure, and the segmentation is achieved through modular package designs that can be independently manufactured and then stacked. This segmentation approach allows for standardized interconnection interfaces between layers, reducing overall system complexity despite the multi-layer configuration.
3Ease of manufacture
If conventional planar package layouts are used, then manufacturing processes are simple, but packaging density and form factor compatibility are limited
Solution Approach 1:
The patent performs preliminary actions by pre-forming conductive vias and interconnection structures within each semiconductor package before the stacking process. The vias are created through the encapsulant material and leadframe structures during the individual package manufacturing process, rather than attempting to create connections after stacking. This preliminary preparation of interconnection pathways significantly simplifies the subsequent stacking and assembly operations, making the complex 3D configuration manufacturable with existing processes.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration allows for increased packaging density and efficient use of space by enabling electrical connection between substrates, facilitating the integration of multiple components and improving form factor compatibility.
Implementation Method 1
These vias are either lined or at least partially filled with a conductive metal material... enabling electrical connection between substrates
Data Source
AI summary
The present invention comprises a semiconductor package comprising a bottom semiconductor package substrate which is populated with one or more electronic components. The electronic component(s) of the bottom substrate are covered or encapsulated with a suitable mold compound which hardens into a package body of the semiconductor package. The package body is provided with one or more vias through the completion of laser drilling process, such via(s) providing access to one or more corresponding conductive contacts of the bottom substrate. These vias are either lined or partially filled with a conductive metal material. Subsequently, a top semiconductor package substrate (which may optionally be populated with one or more electronic components) is mounted to the package body and electrically connected to the conductive metal within the via(s) of the package body.