Stacked IVR Semiconductor Package for Shorter Inductor Paths
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Solution Overview
Problem
Existing semiconductor packages face challenges in reducing size while improving operating characteristics due to the large size of inductors in voltage regulators and increased resistance paths when voltage regulators and passive elements are separately manufactured or disposed on system boards.
Innovation Solution
A semiconductor package is designed with an integrated voltage regulator (IVR) chip and a passive element chip stacked in a front-to-front bonding form, minimizing the distance between the voltage regulator and the inductor, and stacked directly on a logic chip, reducing package size and improving operating characteristics.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If voltage regulator and passive elements are manufactured separately and disposed on system board, then manufacturing flexibility is improved, but package size increases and resistance path increases
Solution Approach 1:
The patent combines the voltage regulator circuit and passive elements (inductor, capacitor) into a single integrated voltage regulator chip using semiconductor fabrication processes. This merging eliminates the need for separate components on the system board, directly reducing package size while maintaining manufacturing efficiency through standardized chip production.
Solution Approach 2:
The patent transitions from a two-dimensional layout of separate components on a system board to a three-dimensional stacked architecture where the IVR chip is vertically stacked above the logic chip. This dimensional change enables miniaturization by utilizing vertical space, reducing the horizontal package footprint by approximately 70%.
2Ease of manufacture
If voltage regulator and passive elements are manufactured separately, then manufacturing cost is reduced, but resistance path increases and operating characteristics deteriorate
Solution Approach 1:
The voltage regulator circuit and passive elements are integrated into a single semiconductor chip, creating direct electrical connections between components. This eliminates the need for external traces and connectors on the system board, significantly reducing resistance and improving signal integrity, while maintaining cost-effectiveness through semiconductor fabrication economies of scale.
Solution Approach 2:
The vertical stacking architecture places the IVR chip directly above the logic chip with minimal interconnection distance. This three-dimensional arrangement reduces the current path length and resistance compared to traditional planar layouts, improving operating characteristics while maintaining manufacturing efficiency.
3Area of stationary object
If inductor size is reduced, then package size is reduced, but inductor performance deteriorates
Solution Approach 1:
The patent implements vertical stacking where the inductor is fabricated on the IVR chip in the third dimension above the logic chip. This three-dimensional placement allows the inductor to maintain adequate size for proper performance while the overall package footprint is reduced by approximately 70% compared to traditional side-by-side component arrangements.
Solution Approach 2:
The inductor is integrated onto the IVR chip rather than being a separate discrete component. This integration allows for optimized inductor design within the chip architecture, maintaining performance characteristics while reducing the overall package size through elimination of external mounting requirements.
4Area of stationary object
If IVR chip is stacked on logic chip, then package size is reduced, but manufacturing complexity increases
Solution Approach 1:
The patent employs wafer-level stacking where multiple wafers are bonded together in a vertical configuration before dicing into individual chips. This approach to three-dimensional integration is performed at the wafer level using established semiconductor bonding techniques, which reduces manufacturing complexity compared to chip-level stacking and enables automated processing.
Data Source
AI summary
A semiconductor package includes a package substrate, a logic chip stacked on the package substrate and including at least one logic element, and a stack structure. The stack structure includes an integrated voltage regulator (IVR) chip including a voltage regulating circuit that regulates a voltage of the at least one logic element, and a passive element chip stacked on the IVR chip and including an inductor.