Stacked LGA Packaging for Eight-Socket One-Hop SMP Topology
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Solution Overview
Problem
Current SMP systems face scalability limitations due to bandwidth bottlenecks and power consumption issues in interconnects, preventing the realization of commercially viable eight-processor, one-hop nodes with sufficient bandwidth.
Innovation Solution
A novel packaging interconnect technology using a stacked land grid array and redistribution card to connect eight processor chips in a one-hop node, increasing interconnect bisection bandwidth and reducing latency, allowing for a two-tier system architecture that quadruples the interconnected processor count.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If buses or crossbar switches are used to interconnect processors in SMP systems, then processors can share common resources, but the bandwidth and power consumption of the interconnect become bottlenecks that limit scalability
Solution Approach 1:
The patent transitions from traditional two-dimensional planar interconnect layouts to a three-dimensional stacked architecture. Processors are arranged in vertical layers and connected via through-silicon vias (TSVs), enabling spatial reuse of interconnect resources and significantly increasing bandwidth without proportionally increasing power consumption. This dimensional change allows eight processors to be interconnected in a one-hop topology, quadrupling the processor count compared to conventional approaches.
2Productivity
If the number of processors in an SMP node is increased to improve compute performance, then system throughput increases, but the interconnect bandwidth required increases proportionally, creating a scalability bottleneck
Solution Approach 1:
The patent implements a nested hierarchical structure where processor cores are nested within processor modules, which are nested within the larger SMP node. Multiple processor modules sharing common interconnect resources through the stacked architecture allows efficient resource utilization. The nested arrangement enables processors to share memory and I/O resources through the three-dimensional interconnect, reducing the total bandwidth requirement compared to fully meshed connections.
3Quantity of substance
If traditional interconnect architectures are used to connect eight processors, then the system can achieve high processor count, but the latency through the interconnect increases due to multiple hierarchical layers
Solution Approach 1:
By stacking processor modules vertically and implementing direct through-silicon via connections, the patent reduces the average path length between any two processors from O(N) in planar architectures to O(1) in the three-dimensional one-hop topology. All processors can reach any other processor in a single hop through the vertical interconnect, eliminating multiple routing layers and significantly reducing latency despite having eight processors in the node.
4Productivity
If the interconnect bandwidth is increased to support more processors, then system throughput improves, but the physical size and complexity of the interconnect structure increases
Solution Approach 1:
The patent achieves high interconnect bandwidth by utilizing the third dimension (vertical space) rather than expanding the planar footprint. Through-silicon vias and vertical interconnect channels provide high-bandwidth pathways between stacked processor modules without requiring large lateral interconnect structures. This vertical integration dramatically increases bandwidth density while minimizing the overall package area.
Data Source
AI summary
A mechanism is provided for packaging a multiple socket, one-hop symmetric multiprocessor topology. The mechanism connects each of a first plurality of processor modules to a first multiple-socket planar via a respective one of a first plurality of land grid array (LGA) connectors. The mechanism connects the first multiple-socket planar to a first side of a redistribution card via a second plurality of LGA connectors. The mechanism connects each of a second plurality of processor modules to a second multiple-socket planar via a respective one of a third plurality of LGA connectors. The mechanism connects the second multiple-socket planar to a second side of the redistribution card via a fourth plurality of LGA connectors.