Stacked Logic-Memory Semiconductor Structure for High-Density Integration
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Solution Overview
Problem
Semiconductor manufacturers face challenges in increasing device density and reducing the dimensions of semiconductor structures due to limited space within electronic devices, which restricts the amount of computing and memory resources.
Innovation Solution
A technique is employed to stack a three-dimensional logic device and a two-dimensional memory device on different layers of a semiconductor structure, using a dielectric structure for electrical insulation and conductive structures for connections, and involving tools like deposition, etching, and planarization to form a semiconductor structure with increased device density.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If logic and memory devices are stacked on different layers to increase device density, then more devices can be placed in limited space, but maintaining electrical insulation and connectivity becomes more difficult
Solution Approach 1:
The patent divides the semiconductor structure into distinct functional layers - logic devices on a first substrate, memory devices on a second substrate, with intermediate dielectric layers and conductive vias. This segmentation allows independent optimization of each layer while maintaining overall system functionality, resolving the contradiction between high device density and electrical insulation requirements.
Solution Approach 2:
The patent introduces intermediate dielectric layers and conductive via structures as mediators between the logic device layer and memory device layer. These intermediary elements provide the necessary electrical insulation while enabling controlled connectivity through vias, thus resolving the contradiction between maintaining insulation and achieving connectivity in stacked architectures.
2Volume of moving object
If the dimensions of semiconductor structures are reduced to conserve space, then more devices fit in electronic devices, but manufacturing precision requirements increase
Solution Approach 1:
The patent transitions from two-dimensional planar integration to three-dimensional stacked architecture. By utilizing the vertical dimension (stacking logic and memory devices on different layers), the design achieves higher device density without proportionally reducing lateral dimensions, thereby managing manufacturing precision requirements while conserving overall device volume.
3Reliability
If multiple dielectric material depositions are performed to ensure proper insulation, then electrical insulation is improved, but manufacturing time and complexity increase
Solution Approach 1:
The patent designs dielectric layers that serve multiple functions simultaneously - providing electrical insulation between logic and memory devices, serving as mechanical support structures, and acting as etch stop layers during fabrication. This multi-functionality reduces the number of separate deposition steps needed, thereby improving manufacturing efficiency while maintaining reliable electrical insulation.
Data Source
AI summary
Some implementations described herein provide a semiconductor structure. The semiconductor structure may include a logic device disposed, at a first side of the logic device, on a carrier wafer of the semiconductor structure. The semiconductor structure may include a dielectric structure disposed on a second side of the logic device, the second side being opposite the first side. The semiconductor structure may include a memory device formed on the dielectric structure.