Stacked Logic Wafer Structure With Fine-Pitch TSV Interconnects
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Solution Overview
Problem
Existing integrated circuit devices face limitations in processing power and efficiency due to the constraints of a single die structure, with challenges in communication latency and bandwidth, particularly in high-performance applications like machine learning work accelerators.
Innovation Solution
A method of manufacturing stacked integrated circuit devices by bonding and thinning logic wafers with through silicon vias (TSVs) to create a multi-layered structure, allowing for increased connectivity and reduced latency with finer pitch TSVs, and incorporating capacitive elements for decoupling.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Power
If a single die structure is used, then the device complexity is low, but the processing power and communication bandwidth are limited
Solution Approach 1:
The patent transitions from a two-dimensional single die structure to a three-dimensional stacked structure by bonding multiple logic dies vertically. This dimensional change enables increased processing power through multiple processing units while maintaining compact footprint, directly resolving the contradiction between processing power and device structure complexity.
Solution Approach 2:
The patent divides the integrated circuit into multiple separate logic dies, each containing independent processing units, memory, and I/O circuits. These segmented dies are then bonded together in a stack, allowing each die to be optimized independently while collectively providing enhanced processing power and communication capabilities.
2Loss of time
If a single die structure is used, then the manufacturing process is simple, but the communication latency is high and bandwidth is limited
Solution Approach 1:
By stacking logic dies vertically and implementing through-die vias for direct vertical interconnects, the patent reduces communication path length between processing units on different dies. This three-dimensional interconnection approach significantly decreases communication latency compared to traditional planar layouts, while the modular stacking process maintains manufacturing feasibility.
3Manufacturing precision
If logic dies are thinned to enable finer pitch TSVs, then the TSV pitch is reduced and connectivity is improved, but the structural support is compromised
Solution Approach 1:
The patent performs wafer thinning operations after the wafers are bonded together in the stacked configuration. By maintaining the full thickness of individual wafers during bonding, sufficient structural support is preserved to enable precise TSV formation with finer pitch. The thinning is then executed in a controlled manner that maintains mechanical integrity throughout the process.
4Power
If multiple logic dies are stacked, then the processing power increases, but the number of additional capacitors required increases
Solution Approach 1:
The patent integrates decoupling capacitor functionality directly into the logic die structure, allowing the same die to serve both as a processing unit and as a source of decoupling capacitance. This multi-functional approach eliminates the need for separate dedicated capacitor dies, reducing the total number of components while maintaining adequate decoupling for the enhanced processing power.
Data Source
AI summary
The first logic wafer is attached to a supporting wafer, which adds sufficient depth to this bonded structure such that the first logic wafer may be thinned during the manufacturing process. The first logic wafer is thinned such that the through silicon vias may be etched in the substrate of the first logic wafer so as to provide adequate connectivity to a second logic wafer, which is bonded to the first logic wafer. The second logic wafer adds sufficient depth to this bonded structure to allow the supporting wafer to then be thinned to enable through silicon vias to be added to the supporting wafer so as to provide appropriate connectivity for the entire stacked structure. The thinned supporting wafer is retained in the finished stacked wafer structure and may comprise additional components (e.g. capacitors) supporting the operation of the processing circuitry in the logic wafers.