Stacked Mask Structure for Semiconductor Feature Patterning
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Solution Overview
Problem
Conventional semiconductor fabrication methods face challenges in achieving precise control and increased density of features due to limitations in overlay accuracy and resolution, particularly as feature sizes decrease, leading to interference in subsequent processes during mask pattern removal.
Innovation Solution
A method involving a stacked structure of two mask layers with different material compositions and ratios, where a sacrificial layer and spacer patterns are used to form mandrels and transfer patterns into a target layer, allowing for etching selectivity and thickness differences to create a battlement-like structure that minimizes interference during mask pattern removal, thereby improving semiconductor device integrity and performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If conventional single patterning process is used, then process simplicity is maintained, but manufacturing precision and feature density are limited due to overlay accuracy and resolution bottlenecks
Solution Approach 1:
The patent divides the patterning process into multiple stages using a stacked mask structure with first and second mask layers. Each layer is patterned separately through lithography and etching processes, enabling precise feature formation that overcomes the resolution limits of single patterning while maintaining process modularity
Solution Approach 2:
The patent transitions from planar single-layer masking to three-dimensional stacked mask architecture. The vertical stacking of multiple mask layers with different material compositions enables additional pattern definition capability, allowing precise control of feature sizes and densities that cannot be achieved with conventional single-layer approaches
2Ease of manufacture
If mask patterns are completely removed after pattern transfer, then process steps are simplified, but subsequent processes are affected by interference and integrity is compromised
Solution Approach 1:
The patent selectively removes only the sacrificial layer material from the stacked mask structure after pattern transfer, while retaining the first and second mask layers. This extraction approach eliminates interference from completely removing all mask patterns while preserving the structural integrity needed for subsequent fabrication processes
Solution Approach 2:
The retained mask layers serve as intermediary protective structures during subsequent processing steps. These mask remnants act as mediators that protect underlying features while allowing necessary process access, preventing direct interference that would occur with complete mask removal
3Productivity
If feature sizes are decreased to increase device density, then device performance is improved, but overlay accuracy and resolution requirements push beyond lithographic limits
Solution Approach 1:
The patent performs preliminary patterning of the first mask layer before forming the second mask layer. This sequential approach allows each lithography step to work with relaxed resolution requirements, building complex high-density patterns through multiple coarser steps rather than requiring a single high-precision lithography operation
Solution Approach 2:
The patent changes material parameters by using different material compositions in the first and second mask layers with varying etch selectivities. This enables precise feature size control through selective etching processes, achieving high-density patterns with accurate dimensions without being constrained by lithographic resolution limits
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enhances the integrity and performance of semiconductor devices by avoiding interference in subsequent processes and achieving better pattern transfer and structure formation, even at smaller feature sizes.
Implementation Method 1
the etching selectivity between two stacked mask layers, as well as the thickness differences between the two stacked mask layers and other layers, to etch the bottom layer of the two stacked mask layers into a battlement-like structure
Data Source
AI summary
A method of forming a semiconductor memory device includes following steps. First of all, a target layer is provided, and a mask structure is formed on the target layer, with the mask structure including a first mask layer a sacrificial layer and a second mask layer. The first mask layer and the second mask layer include the same material but in different containing ratio. Next, the second mask layer and the sacrificial layer are patterned, to form a plurality of mandrels. Then, a plurality of spacer patterns are formed to surround the mandrels, and then transferred into the first mask layer to form a plurality of opening not penetrating the first mask layer. Finally, the first mask layer is used as a mask to etch the target layer, to form a plurality of target patterns.