Stacked Semiconductor Master-Slave Memory Architecture
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
As process technology scales down below 50 nm, it becomes challenging to develop smaller geometry memory devices, especially flash memories, due to worsening transistor characteristics and reliability issues, necessitating new approaches for increasing memory capacity without excessive investment.
Innovation Solution
A system comprising a stack of two non-volatile memory chips, where one chip (the master) has additional circuitries to generate signals and voltages for both chips, facilitating chip size reduction and improved functionality, with Through-Silicon Vias and flip chip bumping for connectivity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of moving object
If process technology is scaled down below 50 nm to increase memory capacity, then chip size is reduced, but transistor characteristics and reliability deteriorate
Solution Approach 1:
The patent transitions from two-dimensional planar scaling to three-dimensional stacked architecture. Multiple memory chips are stacked vertically and interconnected through Through-Silicon Vias (TSVs), enabling capacity expansion in the vertical dimension rather than continuing to scale down feature sizes in the horizontal plane. This resolves the contradiction by achieving increased capacity without further reducing transistor dimensions below the unreliable 50 nm threshold.
Solution Approach 2:
The memory system is divided into multiple separate chips stacked together, with each chip containing memory cores and shared circuitry. The segmentation allows each chip to be manufactured at optimized process nodes while the stacked configuration achieves the aggregate capacity goal, avoiding the need to scale individual transistors below reliable dimensions.
2Area of moving object
If process technology is scaled down to increase memory capacity, then chip geometry is reduced, but manufacturing costs and development investment increase
Solution Approach 1:
By moving to 3D stacking, the patent achieves capacity increase through vertical integration rather than continued horizontal scaling. This allows manufacturing to leverage existing mature process technologies rather than investing in costly and complex sub-50nm fabrication facilities, thereby reducing manufacturing costs and development investment.
Solution Approach 2:
The master chip contains shared circuitry (such as decoders, controllers, and interface logic) that serves multiple slave chips in the stack. This multi-functional design reduces the total amount of circuitry needed across the system, lowering overall manufacturing complexity and cost compared to having full functionality replicated in each chip.
3Adaptability or versatility
If additional circuitries are added to generate signals and voltages for multiple chips, then device functionality is improved, but chip area increases
Solution Approach 1:
Multiple memory chips are merged into a single stacked system with shared circuitry in the master chip. The TSV interconnections merge the electrical pathways between chips, allowing the shared circuitry to control multiple slave chips through the vertical interconnects, thereby achieving enhanced functionality without proportionally increasing total chip area.
Solution Approach 2:
The master chip acts as an intermediary between the external interface and the multiple slave chips. The shared circuitry in the master chip receives external commands and distributes them to appropriate slave chips through TSVs, enabling complex multi-chip functionality while keeping the area overhead localized to the master chip rather than distributed across all chips.
Data Source
AI summary
A stack that includes non-volatile memory devices is disclosed. One of the non-volatile memory devices in the stack is a master device, and the remaining memory device or devices is a slave device(s).