Stacked Memory Architecture for Higher DRAM Array Efficiency
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Solution Overview
Problem
Conventional DRAM structures require large substrate areas due to the integration of peripheral and storage circuit structures on the same substrate, leading to increased manufacturing costs, volume, and low array efficiency.
Innovation Solution
A memory design where peripheral and storage circuit structures are stacked in separate semiconductor layers, with a dielectric layer in between, allowing for enhanced integration and reduced volume.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If peripheral circuit structure and storage circuit structure are formed on the same substrate, then the manufacturing process is simpler, but the substrate area increases leading to higher manufacturing costs
Solution Approach 1:
The patent transitions from a planar layout to a three-dimensional stacked architecture. The peripheral circuit structure and storage circuit structure are formed on different substrates (first substrate and second substrate respectively) and stacked vertically through an integrated circuit layer, thereby reducing the substrate area while maintaining manufacturing feasibility through sequential processing steps.
Solution Approach 2:
The memory device is divided into separate functional modules on different substrates: the peripheral circuit structure on the first substrate and the storage circuit structure on the second substrate. This segmentation allows each module to be optimized independently and reduces the area required on any single substrate.
2Device complexity
If peripheral circuit structure and storage circuit structure are formed on the same substrate, then the device structure is simpler, but the memory volume increases
Solution Approach 1:
The patent employs vertical stacking to arrange the peripheral circuit structure and storage circuit structure in the thickness direction rather than spreading them out in the plane. This dimensional transition significantly reduces the memory volume while the modular stacked design keeps the overall device structure manageable.
Solution Approach 2:
The integrated circuit layer is disposed between the first and second substrates, nesting the connection functionality within the stacked structure. This nesting approach consolidates multiple components into a compact vertical arrangement, reducing volume without excessive structural complexity.
3Ease of manufacture
If peripheral circuit structure and storage circuit structure are formed on the same substrate, then the layout is simpler, but the array efficiency decreases
Solution Approach 1:
By separating the peripheral circuit structure and storage circuit structure onto different substrates, the patent enables independent optimization of the array region. The storage circuit structure on the second substrate can be densely packed without being constrained by peripheral circuit requirements, thereby improving array efficiency while the segmented layout remains manufacturable.
Solution Approach 2:
The vertical stacking arrangement allows the array region to be fully utilized on the second substrate without wasting space on the first substrate for non-array elements. This dimensional separation maximizes the proportion of active array cells in the overall device, improving array efficiency.
Data Source
AI summary
A memory includes a plurality of semiconductor structures stacked onto one another. Each of the plurality of semiconductor structures include: a first base including a peripheral circuit structure; a first integrated circuit layer disposed on the first base and electrically connected to the peripheral circuit structure; and a second base disposed on the first integrated circuit layer. A first dielectric layer is disposed between the first integrated circuit layer and the second base. The second base includes a storage circuit structure. Each of the first base and the second base includes a semiconductor layer.