Stacked Memory TSV Bus Inversion for Lower Switching Noise
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Solution Overview
Problem
Conventional high bandwidth memory (HBM) devices experience increased power consumption and switching noise due to un-encoded data transmission to memory cores, limiting power delivery and performance.
Innovation Solution
Implementing data bus inversion (DBI) logic to encode and decode data signals across through-silicon vias (TSVs), extending DBI encoding from the memory controller to the memory cores, and using a multi-entry FIFO buffer to rearrange bits non-sequentially, thereby reducing power consumption and switching noise.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Use of energy by moving object
If data is transmitted un-encoded through TSVs to memory cores, then transmission speed is maintained, but power consumption increases and switching noise increases
Solution Approach 1:
The data bus is segmented into multiple independent encodable paths, with DBI encoding applied selectively to specific segments (e.g., DQ[0:7] and DQ[8:15] separately) rather than encoding the entire bus uniformly. This allows power-efficient encoding only where needed while maintaining overall system performance.
Solution Approach 2:
The encoding scheme is made dynamic through the use of an encoding indicator signal that can be changed over time. The system can switch between encoded and un-encoded transmission modes, and between different encoding configurations, allowing adaptation to varying power and performance requirements in different operational contexts.
2Object-generated harmful factors
If DBI encoding is applied to data signals, then power consumption is reduced, but device complexity increases due to encoding/decoding logic
Solution Approach 1:
The data bus is segmented into multiple independent encodable paths, with DBI encoding applied selectively to specific segments (e.g., DQ[0:7] and DQ[8:15] separately) rather than encoding the entire bus uniformly. This allows power-efficient encoding only where needed while maintaining overall system performance.
Solution Approach 2:
A multi-entry FIFO buffer structure is introduced as an intermediary component between the data bus and memory cores. This FIFO buffer handles the complex encoding/decoding operations and timing adjustments, isolating the complexity from the main data path while still achieving noise reduction benefits.
3Reliability
If multi-entry FIFO buffer is used to rearrange bits non-sequentially, then power delivery robustness is improved, but device complexity increases
Solution Approach 1:
The data bus is segmented into multiple independent encodable paths, with DBI encoding applied selectively to specific segments (e.g., DQ[0:7] and DQ[8:15] separately) rather than encoding the entire bus uniformly. This allows power-efficient encoding only where needed while maintaining overall system performance.
Solution Approach 2:
The encoding scheme is made dynamic through the use of an encoding indicator signal that can be changed over time. The system can switch between encoded and un-encoded transmission modes, and between different encoding configurations, allowing adaptation to varying power and performance requirements in different operational contexts.
Data Source
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Figure 3A~3B
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AI summary
An embodiment of a memory apparatus may include a memory core (11), a plurality of through-silicon vias (TSVs) (12), and data bus inversion logic (13) coupled between the memory core (11) and the TSVs (12) to encode and decode a data signal on a signal path through the TSVs (12) in accordance with a data bus inversion of the data signal. Other embodiments are disclosed and claimed.