Stacked Memory Cell Structure With Air Gaps for Cross-Coupling Isolation
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
The integration of semiconductor devices is limited by the area occupied by unit memory cells, and existing three-dimensional semiconductor devices face challenges in improving operational reliability and reducing cross-coupling between stacked memory cells.
Innovation Solution
A semiconductor device structure featuring alternately stacked conductive and insulating layers, a channel layer penetrating the gate structure, memory patterns between the channel and conductive layers, a blocking layer with specific extensions, and air gaps that reduce cross-coupling by isolating memory cells, along with a manufacturing method that forms these components through a series of layering and etching processes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If memory cells are stacked in three-dimensional structure to improve integration, then the degree of integration is improved, but cross-coupling between stacked memory cells increases and operational reliability deteriorates
Solution Approach 1:
The patent divides the gate structure into multiple conductive layers separated by insulating layers, creating distinct segments for different memory cells. This segmentation isolates the electrical fields of adjacent memory cells, preventing cross-coupling while maintaining the three-dimensional stacked structure for high integration.
Solution Approach 2:
The patent introduces insulating layers as intermediary elements between conductive layers of adjacent memory cells. These insulating layers act as mediators that block electrical interference and cross-coupling between stacked memory cells, thereby improving operational reliability while preserving the high-density three-dimensional architecture.
2Ease of manufacture
If conventional single-layer memory cell structure is used, then manufacturing is simpler, but the degree of integration is limited by substrate area
Solution Approach 1:
The patent transitions from a conventional single-layer (two-dimensional) memory cell structure to a multi-layer stacked (three-dimensional) structure. By adding the vertical dimension with multiple conductive and insulating layers, the patent achieves higher integration density without significantly complicating the manufacturing process, as the layering follows standard semiconductor fabrication techniques.
Data Source
AI summary
A semiconductor device includes: a gate structure including conductive layers and insulating layers, which are alternately stacked; a channel layer penetrating the gate structure; memory patterns respectively located between the channel layer and the conductive layers; a blocking layer including first parts located between the memory patterns and the conductive layers, and second parts extending between the memory patterns and protruding toward the insulating layers to the inside of the gate structure; and air gaps including a first region located in the second parts and a second region located between the memory patterns.