Stacked Memory Arrays With Continuous Vias for Higher Density
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Solution Overview
Problem
Conventional memory devices face limitations in memory density due to the constraints of peripheral circuitry occupying valuable surface area, leading to increased process complexity and cost, and the separation of memory cells and peripheral circuitry in different layers is challenging.
Innovation Solution
A vertically-stacked memory design is implemented, where peripheral circuitry is separated to a distinct layer, allowing for greater flexibility in circuit design and increased memory density by freeing up area previously devoted to peripheral circuitry, with memory arrays in a separate layer connected via vias.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If more FEOL transistors are formed on a substrate to increase memory density, then memory cell density improves, but the number of available transistors is limited by substrate constraints and critical dimension scaling complexity
Solution Approach 1:
The patent transitions from a two-dimensional planar memory architecture to a three-dimensional stacked architecture. Multiple memory arrays are stacked vertically across different layers (first memory array in first layer, second memory array in second layer, etc.), connected through vias. This vertical stacking enables increased memory density without further reducing critical dimensions or complicating FEOL processes.
Solution Approach 2:
The memory device is segmented into multiple separate layers, each containing a memory array. The peripheral circuitry is separated from the memory arrays and placed in dedicated layers. This segmentation allows independent optimization of memory cells and peripheral circuits, simplifying the manufacturing process while achieving high density through vertical integration.
2Area of stationary object
If peripheral circuitry is integrated in the same layer as memory arrays, then device area is reduced, but memory density and processing complexity are compromised
Solution Approach 1:
The device is segmented into functionally distinct layers: memory array layers and peripheral circuitry layers. Each memory array is placed in a dedicated layer, with peripheral circuits (decoders, sense amplifiers, I/O buffers) placed in separate layers. This segmentation frees up surface area in memory layers for additional memory cells while maintaining all necessary peripheral functions.
Solution Approach 2:
Peripheral circuitry that would traditionally occupy horizontal space in the same layer as memory arrays is moved to vertical positions in separate layers. Connectors and vias provide vertical interconnection between memory arrays and peripheral circuits, transforming a planar layout constraint into a three-dimensional architecture that achieves both high density and functional integration.
3Quantity of substance
If critical dimensions are decreased to increase transistor density, then memory cell density improves, but manufacturing precision requirements and process complexity increase significantly
Solution Approach 1:
Instead of continuing to scale critical dimensions horizontally, the patent exploits the vertical dimension for density improvement. Multiple memory arrays are stacked in the vertical direction, connected by vias, allowing transistor density to increase through layer multiplication rather than through further miniaturization of individual transistors. This approach avoids the manufacturing precision challenges associated with sub-10nm scaling.
4Quantity of substance
If memory arrays and peripheral circuitry are in separate layers, then memory density and processing are improved, but inter-layer connections and vias are required
Solution Approach 1:
Multiple separate layers containing memory arrays and peripheral circuitry are merged into a single integrated three-dimensional structure. Vias and connectors establish electrical connections between layers, combining the functional benefits of separation (simplified processing, increased density) with the electrical connectivity of integration. This merging occurs through standard semiconductor fabrication processes for multi-layer interconnects.
Data Source
AI summary
Described herein are stacked memory devices that include some peripheral devices for controlling the memory in a separate layer from one or more memory arrays. The layers of the memory device are connected together using vias, which transfer power and data between the layers. In some examples, a portion of the peripheral devices are included in a memory layer, and another portion are included in a peripheral device layer. Multiple layers of memory arrays and/or peripheral devices may be included, e.g., one peripheral device layer may control multiple layers of memory arrays, or different layers of memory arrays may have dedicated peripheral device layers. Different types of memory arrays, such as DRAM or SRAM, may be included.