Stacked Memory ECC for TSV Transmission Error Correction
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Solution Overview
Problem
In stacked chip structures, such as 2.5D and 3D chip configurations, errors during data read operations can occur due to malfunctioning memory dies or transmission signal noise through silicon via (TSV) lines, necessitating effective error detection and correction mechanisms to distinguish between die-based errors and transmission errors.
Innovation Solution
A semiconductor memory device with a stacked structure incorporating first and second type error correction coding (ECC) circuits, where the first type ECC circuit generates transmission parity bits at memory dies and the second type ECC circuit, located in the buffer die, detects and corrects transmission errors using these parity bits, effectively addressing soft data failures caused by TSV line noise.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If data is transmitted through TSV lines in stacked chip structure, then memory capacity and operation speed are improved, but transmission errors occur due to noise
Solution Approach 1:
The first type ECC circuit generates transmission parity bits in advance before data is transmitted through TSV lines. This preliminary action prepares error correction capability beforehand, allowing the system to maintain high transmission speed while protecting against noise-induced errors during data transfer between stacked memory dies
Solution Approach 2:
The second type ECC circuit in the buffer die detects transmission errors using the pre-generated parity bits and corrects them by generating corrected data. This feedback mechanism ensures that errors introduced during high-speed transmission through TSV lines are automatically detected and corrected, maintaining transmission reliability without sacrificing speed
2Reliability
If error detection and correction mechanisms are added, then transmission reliability is improved, but device complexity increases
Solution Approach 1:
The error correction function is segmented into two distinct types of ECC circuits: the first type ECC circuit in memory dies that generates parity bits, and the second type ECC circuit in the buffer die that detects and corrects errors. This segmentation distributes the complexity across different components rather than concentrating it in one location, making the overall system more manageable and modular
Solution Approach 2:
Transmission parity bits act as an intermediary element between the memory dies and buffer die. These parity bits carry error detection and correction information without requiring complex real-time processing during transmission, thereby improving reliability while keeping the circuit complexity manageable through the use of this intermediate data structure
Data Source
AI summary
The semiconductor memory device includes first group dies including at least one buffer die, and second group dies including a plurality of memory dies stacked on the first group dies and conveying data through a plurality of TSV lines. Here, at least one of the plurality of memory dies includes a first type ECC circuit which generates transmission parity bits using transmission data to be transmitted to the first group die, and the buffer die includes a second type ECC circuit which corrects, when a transmission error occurs in the transmission data received through the plurality of TSV lines, the transmission error using the transmission parity bits and generates error-corrected data.