Stacked Memory Die Identifier Logic for Unique Chip IDs

Solution Overview

Problem

Conflicts arise during the manufacturing of three-dimensional memory stacks due to identical chip identifiers assigned before stacking, leading to issues with memory chips having the same identifier.

Innovation Solution

A semiconductor device with identifier generation circuits in each die that automatically generate unique chip identifiers based on auxiliary input signals and neighboring die identifiers, using logic gates for logical operations.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Ease of manufacture

If chip identifiers are set before stacking, then manufacturing process is simplified, but identifier conflicts occur between different memory chips

Engineering Contradiction:

Improvemanufacturing process simplicityVSAvoididentifier uniqueness

Core Design Contradiction:

Ease of manufactureVSReliability

Solution Approach 1:

The patent applies preliminary action by pre-configuring identifier generation circuits and auxiliary input signals in each die before stacking. The bottom die's identifier is generated first, then transmitted to upper dies through TSVs, enabling automatic sequential generation without manual configuration. This resolves the contradiction by maintaining manufacturing simplicity while ensuring identifier uniqueness through automated generation based on die position.

Inventive Principle:

Principle #10Preliminary action

Solution Approach 2:

The patent implements feedback by transmitting the generated identifier from the bottom die through TSVs to upper dies. Each upper die receives the identifier from the lower die as input, uses it with its auxiliary input signal to generate a new unique identifier. This feedback mechanism ensures identifier uniqueness across all stacked dies while keeping the manufacturing process simple.

Inventive Principle:

Principle #23Feedback

2Reliability

If manual identifier assignment is used, then identifier uniqueness can be ensured, but manufacturing complexity and time increase

Engineering Contradiction:

Improveidentifier uniquenessVSAvoidmanufacturing process complexity

Core Design Contradiction:

ReliabilityVSDevice complexity

Solution Approach 1:

The patent applies self-service by enabling each die to automatically generate its own unique identifier using its identifier generation circuit and auxiliary input signal. The bottom die generates its identifier independently, then transmits it to upper dies which use it to generate their own identifiers. This eliminates manual identifier assignment while ensuring uniqueness, reducing manufacturing complexity and automation time.

Inventive Principle:

Principle #25Self-service

3Reliability

If manual identifier assignment is used, then identifier uniqueness can be ensured, but manufacturing time increases

Engineering Contradiction:

Improveidentifier uniquenessVSAvoidmanufacturing speed

Core Design Contradiction:

ReliabilityVSProductivity

Solution Approach 1:

The patent applies preliminary action by pre-configuring identifier generation circuits and auxiliary input signals in each die before stacking. The bottom die's identifier is generated first, then transmitted to upper dies through TSVs, enabling automatic sequential generation without manual configuration. This resolves the contradiction by maintaining manufacturing simplicity while ensuring identifier uniqueness through automated generation based on die position.

Inventive Principle:

Principle #10Preliminary action

Solution Approach 2:

The patent implements continuity of useful action by establishing continuous electrical connections through TSVs between identifier generation circuits of stacked dies. The identifier generation process flows continuously from the bottom die through intermediate dies to the top die, eliminating interruptions and manual intervention. This ensures identifier uniqueness while maintaining high manufacturing productivity.

Inventive Principle:

Principle #20Continuity of useful action

Data Source

PatentUS20260026399A1Semiconductor device, memory device, and method for automatically generating chip identifiers for semiconductor dies in stacked structure using logic gates

Publication Date: 2026.01.22 NAN YA TECH

AI summary

A method for automatically generating chip identifier for semiconductor dies in a stacked structure is provided. The method includes the following steps: obtaining a first semiconductor die and a second semiconductor die, wherein the first semiconductor die and the second semiconductor die include a first identifier generation circuit and a second identifier generation circuit, respectively; forming a stacked structure by stacking the second semiconductor die on the first semiconductor die, wherein the first identifier generation circuit is electrically connected to the second identifier generation circuit; and generating a first chip identifier and a second chip identifier for the first semiconductor die and the second semiconductor die by the first identifier generation circuit and the second identifier generation circuit, respectively. The second chip identifier is generated using the first chip identifier and an auxiliary input signal.