Stacked 3D Memory Interconnect Layer Stress Relaxation
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Solution Overview
Problem
As the number of layers in a stacked semiconductor memory device increases, there is a concern over degradation due to stress-related issues such as failure, peeling, cracking, or warping, which affects the device's reliability and performance.
Innovation Solution
The semiconductor memory device incorporates an interconnect layer with a silicon portion and a metal portion, where the first metal layer is connected to the interconnect layer via a contact portion, and the second metal layer is connected to the first metal layer, allowing for stress relaxation and reduced resistance, thereby suppressing device degradation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If the number of layers in the stacked body increases to enhance memory capacity, then storage density is improved, but stress-related degradation (failure, peeling, cracking, warping) worsens
Solution Approach 1:
The patent applies composite materials by combining silicon and metal in a stacked configuration within the interconnect layer. The silicon portion provides mechanical strength and stress resistance, while the metal portion provides electrical conductivity. This composite structure enables the device to maintain both high memory capacity through increased layering and high reliability through stress management.
Solution Approach 2:
The patent changes the physical and material parameters of the interconnect layer by introducing a multi-material stacked structure with different mechanical and electrical properties. The silicon portion has high mechanical strength but lower conductivity, while the metal portion has high conductivity but lower mechanical strength. By adjusting the configuration and properties of these materials, the device achieves both high capacity and high reliability.
2Quantity of substance
If the number of layers in the stacked body increases to enhance memory capacity, then storage density is improved, but device degradation (failure, peeling, cracking, warping) worsens
Solution Approach 1:
The patent uses composite materials in the interconnect layer, stacking silicon and metal to create a structure that combines the high mechanical strength of silicon with the electrical conductivity of metal. This composite approach allows the device to achieve high storage density through increased layering while maintaining device strength through the silicon portion's mechanical properties.
Solution Approach 2:
The patent segments the interconnect layer into distinct silicon and metal portions, each performing specific functions. The silicon portion is configured to primarily provide mechanical strength and stress resistance, while the metal portion provides electrical conductivity. This segmentation allows each material to optimize its contribution to overall device performance.
3Loss of energy
If the interconnect layer uses metal to reduce resistance, then electrical conductivity is improved, but stress resistance deteriorates
Solution Approach 1:
The patent applies composite materials by stacking silicon and metal in the interconnect layer. The metal portion provides low electrical resistance for efficient current flow, while the silicon portion provides high mechanical strength and stress resistance. This composite structure resolves the contradiction between electrical conductivity and stress resistance.
Solution Approach 2:
The patent segments the interconnect layer into functionally distinct portions: a metal portion optimized for electrical conductivity with low resistance, and a silicon portion optimized for mechanical strength and stress resistance. This segmentation allows each material to excel at its primary function without compromising the other.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration effectively relaxes stress and reduces resistance in the interconnect layer, even as the number of layers increases, thereby suppressing device degradation and maintaining performance.
Implementation Method 1
The interconnect layer includes: a first portion including silicon; and a second portion provided on the first portion and including metal
Implementation Method 2
The first metal layer is provided on the first contact portion and extends in the first direction, the first metal layer is electrically connected to the interconnect layer via the first contact portion
Data Source
AI summary
According to one embodiment, a semiconductor memory device includes a substrate; a stacked body provided on the substrate and including a plurality of electrode layers; a semiconductor film; a charge storage film; an interconnect layer provided in the stacked body, the interconnect layer; a first contact portion; a first metal layer; and a second metal layer. The interconnect layer includes: a first portion including silicon; and a second portion provided on the first portion and including metal. The first metal layer is provided on the first contact portion. The second metal layer is provided on the first metal layer, and electrically connected to the interconnect layer.