Stacked Variable-Resistance Memory for Leakage-Safe Programming
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Solution Overview
Problem
Current semiconductor memory devices face challenges in achieving miniaturization, low power consumption, high performance, and diversification while maintaining reliable memory cell operations, particularly in storing data using resistance phase switching characteristics.
Innovation Solution
The proposed electronic device incorporates variable resistance layers and insulating layers alternately stacked with conductive pillars and slit insulating layers, where the variable resistance layers remain in an amorphous state during programming, enabling efficient data storage through resistance changes without phase transitions.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If variable resistance layers undergo phase transitions during programming, then data storage capability is improved, but leakage current occurs in unselected memory cells
Solution Approach 1:
The patent changes the physical state parameter of the variable resistance layer from crystalline to amorphous. This parameter change prevents phase transitions during programming operations, thereby eliminating leakage current in unselected memory cells while maintaining data storage capability through resistance changes.
Solution Approach 2:
Instead of using the conventional approach where phase transitions (crystalline to amorphous) enable data storage, this patent inverts the approach by using amorphous state variable resistance layers that change resistance without phase transitions. This inversion eliminates the harmful side effect of leakage current while preserving the useful function of data storage.
2Reliability
If conventional phase-change memory structures are used, then data storage is achieved through phase transitions, but manufacturing complexity increases
Solution Approach 1:
The patent extracts the phase transition mechanism from the data storage function. By removing the crystalline phase and keeping only the amorphous state with resistance-changing capability, the structure is simplified while maintaining data storage reliability. The harmful phase transition process is taken out, leaving only the useful resistance change function.
3Area of moving object
If miniaturization is pursued in semiconductor memory devices, then device density is improved, but maintaining reliable memory cell operations becomes difficult
Solution Approach 1:
The patent applies parameter changes by transitioning from crystalline to amorphous variable resistance layers, which eliminates phase transitions and leakage currents. This enables reliable memory cell operations even as device dimensions are reduced for miniaturization, as the amorphous state provides stable resistance characteristics without the need for precise phase control.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration improves the operating characteristics and reliability of memory cells by allowing selective programming and preventing leakage current in unselected cells, enhancing read performance and operational efficiency.
Implementation Method 1
The variable resistance layers may remain in an amorphous state during a program operation
Data Source
AI summary
A semiconductor memory includes first variable resistance layers and insulating layers alternately stacked; conductive pillars passing through the first variable resistance layers and the insulating layers; a slit insulating layer vertically passing through the insulating layers, extending in a first direction, and being disposed in a second direction of the insulating layers, the second direction intersecting with the first direction; conductive layers disposed between the slit insulating layer and the first variable resistance layers; and electrode layers disposed between the conductive layers and the first variable resistance layers. The first variable resistance layers remain in an amorphous state during a program operation.