Stacked Microelectronic Memory Structure for Denser Logic Integration
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Solution Overview
Problem
Microelectronic device designers face challenges in reducing feature dimensions and separation distances while maintaining performance and simplifying fabrication, particularly due to processing conditions affecting control logic devices in memory devices like DRAM, which impede size reduction and performance improvements.
Innovation Solution
A method for forming microelectronic devices that includes configuring control logic devices within memory arrays to be vertically offset from memory cells, using horizontal areas for array regions, digit line exit regions, word line exit regions, and socket regions to facilitate electrical connections, allowing for compact and efficient device design.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Length of moving object
If control logic devices are formed using conventional processing conditions, then the memory array can be formed, but the control logic devices limit the reduction of feature dimensions and separation distances
Solution Approach 1:
The device is divided into two separate semiconductor structures: a first structure containing the memory array and a second structure containing the control logic devices. This segmentation allows each structure to be optimized independently for its specific function, enabling the memory array to use smaller feature dimensions while the control logic devices can operate under their required processing conditions.
Solution Approach 2:
The patent transitions from a planar arrangement to a three-dimensional stacked configuration by attaching the second semiconductor structure to the first structure. This vertical stacking enables simultaneous optimization of both memory array density and control logic device performance without compromising either.
2Area of stationary object
If conventional control logic device configurations are used, then the memory array can be controlled, but the horizontal footprint of socket regions increases
Solution Approach 1:
The patent moves control logic devices from a planar layout to a vertical stack configuration. By attaching the second semiconductor structure containing control logic devices to the first structure, the horizontal footprint is dramatically reduced while connectivity is maintained through vertical attachment interfaces and conductive pathways.
Solution Approach 2:
The control logic devices are effectively nested within the vertical stack above the memory array. This nested configuration allows both functional blocks to coexist in a compact volume, with the control logic devices positioned vertically above rather than laterally adjacent to the memory cells.
3Quantity of substance
If feature dimensions are reduced to increase density, then areal density improves, but processing conditions become more difficult to control
Solution Approach 1:
By segmenting the device into two separate semiconductor structures that are processed independently and then attached, the patent allows the memory array structure to be fabricated with smaller, more densely packed features while the control logic devices can be processed under more relaxed conditions. This independent processing resolves the manufacturing difficulty associated with controlling small feature dimensions.
Data Source
AI summary
A method of forming a microelectronic device comprises forming a first microelectronic device structure comprising a first semiconductor structure, control logic circuitry including transistors at least partially overlying the first semiconductor structure, and a first isolation material covering the first semiconductor structure and the control logic circuitry. A second microelectronic device structure comprising a second semiconductor structure and a second isolation material over the second semiconductor structure is formed. The second isolation material of the second microelectronic device structure is bonded to the first isolation material of the first microelectronic device structure to attach the second microelectronic device structure to the first microelectronic device structure. Memory cells comprising portions of the second semiconductor structure are formed after attaching the second microelectronic device structure to the first microelectronic device structure. Microelectronic devices, electronic systems, and additional methods are also described.