Stacked Memory Access Control for OTP Testing After Chip Bonding
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Solution Overview
Problem
Existing stacked memory devices face challenges in controlling non-volatile memory circuits and directly accessing memory units after bonding with logic chips, especially when the number of memory units varies, making it difficult to manage OTP circuits and perform tests.
Innovation Solution
The solution involves a stacked memory device configuration with a logic chip, memory chip, and an external port module, incorporating a non-volatile memory circuit, memory controller, peripheral controller, shifters, and selectors, allowing for controlled access and testing of memory units through a reset procedure, memory test mode, and non-volatile memory operation mode.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If memory chip is bonded to logic chip in stacked configuration, then integration density is improved, but direct access to memory units and control of OTP circuit becomes difficult
Solution Approach 1:
The patent segments the control functions by introducing a peripheral controller that operates independently from the memory controller. This peripheral controller can directly access memory units and control OTP circuits even when the memory chip is bonded to the logic chip, thus maintaining ease of operation while achieving high integration density through stacking.
Solution Approach 2:
The peripheral controller acts as an intermediary between external sources and the memory units/OTP circuit. It receives commands from external sources via external ports and translates them into appropriate control signals for the memory units and OTP circuit, enabling indirect access that bypasses the bonding limitation.
2Adaptability or versatility
If number of memory units is varied to match logic chip requirements, then adaptability is improved, but control complexity of OTP circuit increases
Solution Approach 1:
The peripheral controller is designed with universal functionality to handle various numbers of memory units through configurable shift amounts. It can adapt to different logic chip requirements by adjusting the shift amount parameter, providing a unified control interface that simplifies OTP circuit control regardless of the number of memory units.
Solution Approach 2:
The system employs dynamic configuration where the peripheral controller can adjust its operation parameters (such as shift amounts) based on the specific number of memory units required. This dynamic adaptability allows the same hardware structure to serve different configurations without increasing control complexity.
3Area of stationary object
If memory chip is cut from memory wafer to match logic chip size, then area efficiency is improved, but direct testing capability is lost
Solution Approach 1:
The peripheral controller serves as an intermediary that enables direct testing capability even after the memory chip is cut and bonded. It provides a testing mode that can be activated through external ports, allowing test commands to be sent directly to memory units for verification without requiring access to the original wafer structure.
Solution Approach 2:
The peripheral controller includes built-in testing functionality that can perform tests before the memory chip is permanently integrated into the logic chip. This preliminary testing capability allows verification of memory units immediately after cutting and bonding, ensuring quality control while maintaining area efficiency.
Data Source
AI summary
A stack memory device and its operation method are provided. The stack memory device includes a memory chip having memory units, a logic chip bonded to the memory chip and an external port module. The logic chip has an OTP circuit storing operation information of the memory units; a memory controller, a peripheral controller, shifters, and selectors. Each o shifter receives a command, data and address from the peripheral controller, and transfers the command, data and address to each memory unit with a shift amount with respect to a clock signal. The peripheral controller is in a standby status when the stacked memory device is in an operation status, or the peripheral controller performs a memory test or controls of the non-volatile memory circuit.