Stacked Memory Package Structure Without Substrate Expansion
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Solution Overview
Problem
Existing memory system packaging technologies result in an overall package size increase of at least 30% compared to the memory chip itself, hindering the development of smaller packaging solutions.
Innovation Solution
A memory system package structure that includes a memory chip, memory controller, and a redistribution layer, where the memory controller is stacked on the memory chip with the redistribution layer on the opposite side, eliminating the need for a substrate and allowing direct electrical connection without a bonding layer, thus reducing the package size and cost.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If existing packaging technology is used to wrap memory chip and memory controller with housing, then electrical connection and protection are ensured, but overall package size increases by at least 30% compared with memory chip size
Solution Approach 1:
The patent merges the memory controller directly onto the memory chip substrate, eliminating the need for a separate substrate and housing structure. The memory controller is positioned on the back surface of the memory chip, with electrical connections established through through-silicon vias (TSVs) that penetrate the chip substrate. This integration approach combines two previously separate components (memory chip and memory controller) into a single unified structure, thereby ensuring electrical connection and protection while dramatically reducing package size.
Solution Approach 2:
The patent transitions from a planar packaging arrangement to a three-dimensional stacked architecture. By placing the memory controller on the back surface of the memory chip and using vertical through-silicon vias for electrical connection, the design exploits the third dimension (depth/vertical direction) to establish electrical pathways. This dimensional change eliminates the need for lateral expansion through housing and wiring boards, thereby reducing overall package volume while maintaining reliable electrical connections.
2Reliability
If substrate and bonding layer are used for connecting memory chip and memory controller, then electrical connection is achieved, but package area and cost increase
Solution Approach 1:
The patent extracts and eliminates the substrate and bonding layer from the packaging structure. Instead of using a separate substrate to mount both the memory chip and memory controller, the design uses the memory chip's own substrate as the mounting platform for the memory controller. The traditional wire bonding process is replaced with through-silicon via technology that creates direct electrical pathways through the chip substrate, removing unnecessary intermediate layers and reducing package area.
Solution Approach 2:
The patent introduces through-silicon vias (TSVs) as intermediary conductive structures that directly connect the memory controller on the back surface to the memory chip circuits on the front surface. These TSVs act as mediators that establish electrical connections through the chip substrate without requiring external substrates or bonding wires, thereby reducing package area while ensuring reliable electrical connection.
3Ease of manufacture
If traditional packaging structure with substrate is used, then manufacturing is simplified, but package size and cost increase
Solution Approach 1:
The patent combines the memory controller fabrication process with the memory chip manufacturing process. Both components are fabricated using standard semiconductor manufacturing techniques on the same substrate, allowing for batch processing and integration in a single manufacturing flow. This merging of fabrication processes maintains manufacturing simplicity while eliminating the need for separate substrate assembly and wire bonding steps, thereby reducing package volume.
Data Source
AI summary
A memory system package structure and a manufacturing method thereof are disclosed. For example, the memory system package structure can include a memory chip, a memory controller and a distribution layer. The memory chip can include a first surface. The memory controller can be positioned on the first surface. The redistribution layer can be positioned on a side of the memory controller facing away from the memory chip. The memory chip and the memory controller can be electrically connected with the redistribution layer.