Stacked Semiconductor Memory with Parallel Electrode Pads
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Current semiconductor memory apparatus face challenges in achieving both miniaturization and increased capacity due to limitations in stacking semiconductor memory devices and controllers on a wiring substrate, particularly in maintaining efficient electrical connections while minimizing size and maximizing memory density.
Innovation Solution
The semiconductor memory apparatus employs a wiring substrate with device mounting parts and connection pads aligned along exterior sides, where semiconductor memory devices and a controller are stacked with electrode pads arranged in a specific configuration, connected by metallic wires to facilitate efficient electrical connections and allow for alternating stacking of memory devices, thereby optimizing space and capacity within the micro SD card dimensions.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If semiconductor memory devices are stacked on a wiring substrate to increase capacity, then memory capacity is improved, but the device size and complexity of electrical connections worsen
Solution Approach 1:
The patent divides the connection system into distinct segments: first metallic wires connect memory device electrode pads to substrate connection pads, second metallic wires connect controller electrode pads to substrate connection pads, and third metallic wires connect memory device electrode pads to controller electrode pads. This segmentation organizes the complex electrical connections into manageable, functionally-separated components, making the overall system easier to manufacture and test while enabling higher memory capacity through stacked devices.
2Quantity of substance
If more semiconductor memory devices are stacked to increase capacity, then memory capacity is improved, but the area occupied by connection pads increases
Solution Approach 1:
The patent transitions from a two-dimensional layout where connection pads would spread across the substrate surface to a three-dimensional stacked configuration. Memory devices are vertically stacked with electrode pads arranged in multiple layers, connected via metallic wires that extend through the vertical dimension. This dimensional change allows increased memory capacity without proportionally increasing the substrate area occupied by connection pads, as connections are routed through the vertical stacking direction rather than spreading horizontally.
3Volume of moving object
If semiconductor memory devices are miniaturized to reduce card size, then device size is improved, but manufacturing precision and connection reliability worsen
Solution Approach 1:
The patent employs specific parameter specifications to maintain manufacturing precision despite miniaturization: metallic wires with controlled diameters (5-20 micrometers), electrode pads with defined dimensions, and controlled wire lengths for each connection type. These parameter changes establish precise manufacturing tolerances and geometric constraints that ensure connection reliability even as overall device size is reduced for smaller card formats.
Data Source
AI summary
The semiconductor memory apparatus related to an embodiment of the present invention includes a wiring substrate arranged with a device mounting part and connection pads aligned along one exterior side of the wiring substrate, a plurality of semiconductor memory devices including electrode pads which are arranged along one external side of the wiring substrate, a semiconductor memory device group in which the plurality of semiconductor memory devices are stacked on the device mounting part of the wiring substrate so that pad arrangement sides all face in the same direction, and a controller device including the electrode pads arranged along at least one external side of the wiring substrate, wherein the electrode pads of the plurality of semiconductor memory devices and the electrode pads of the controller device are arranged parallel to an arrangement position of the connection pads of the wiring substrate.