Stacked Memory Die Layout Using Passive TSV Interposers
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Solution Overview
Problem
The integration of multiple tiers of memory dies in stacked semiconductor devices, such as High Bandwidth Memory (HBM), is hindered by complex networks of Through-Silicon Vias (TSVs) that increase die size, manufacturing costs, and design complexity, limiting scalability and feasibility for future designs.
Innovation Solution
The Terraced Chiplet Cubing (TCC) technology uses an economical silicon interposer to replace TSVs with passive dies that include through-silicon vias, allowing core dies to be connected without TSVs, enabling a modular and scalable design with reduced manufacturing costs and improved active silicon utilization.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If Through-Silicon Vias (TSVs) are used for vertical interconnects in stacked memory dies, then electrical connection between tiers is achieved, but die size increases and manufacturing costs escalate
Solution Approach 1:
The patent introduces an interposer substrate as an intermediary component between stacked memory dies. The interposer contains through-silicon vias that establish vertical interconnects, while the memory dies themselves remain free of TSVs. This mediator approach allows electrical connection between tiers without requiring the memory dies to contain TSVs, thereby achieving reliable electrical connection while preventing die size increase.
2Reliability
If Through-Silicon Vias (TSVs) are integrated into memory dies for vertical interconnects, then electrical connection between stacked tiers is enabled, but manufacturing costs increase
Solution Approach 1:
The interposer substrate serves as a mediator that consolidates the TSV manufacturing complexity into a single component rather than requiring TSV fabrication in each memory die. This approach enables vertical interconnects while reducing manufacturing costs by eliminating the need for expensive TSV processes on the memory dies themselves.
Solution Approach 2:
The patent segments the vertical interconnect function from the memory die structure, placing TSVs in the interposer substrate while keeping memory dies free of TSVs. This segmentation allows the complex TSV manufacturing to be isolated to a dedicated component, simplifying the overall manufacturing process and reducing costs.
3Reliability
If TSVs and Redistribution Layers are designed for multiple memory tiers, then vertical interconnection is achieved, but design complexity and photolithography mask costs increase
Solution Approach 1:
The interposer substrate acts as a mediator that handles all the complex TSV and Redistribution Layer design for vertical interconnection. This allows the memory dies to maintain simpler, more standard designs while the interposer manages the complexity of multi-tier vertical interconnection and signal routing.
Solution Approach 2:
Instead of placing TSVs and complex Redistribution Layers directly in the memory dies, the patent inverts the approach by placing these complex interconnect structures in the interposer substrate. This inversion simplifies the memory die design while achieving the same vertical interconnection functionality.
Data Source
AI summary
In some aspects, a semiconductor device is provided. The semiconductor device includes a plurality of core dies; and a plurality of passive dies, each of the plurality of passive dies corresponding to one respective core die of the plurality of core dies, wherein each of the plurality of passive dies comprises a plurality of through-silicon vias configured to connect the plurality of core dies with a controller die, and wherein the plurality of core dies and the plurality of passive dies are arranged vertically into first to Nth tiers in a manner that each tier of the first to Nth tiers includes a core die of the plurality of core dies and a corresponding passive die of the plurality of passive die placed side-by-side horizontally.