Stacked Memory Pillars Seamless Connection via Sacrificial Layer
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Solution Overview
Problem
Current semiconductor memory technologies face challenges in efficiently connecting stacked memory pillars, leading to increased contact resistance and reduced current flow between bit lines and source lines, which affects memory performance and manufacturing yield.
Innovation Solution
A manufacturing method involving a sacrifice layer and conductive layer replacement process is used to form a seamless connection between stacked memory pillars, reducing contact resistance and improving current flow by forming a continuous conductive layer that connects the pillars.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional connection methods are used for stacked memory pillars, then manufacturing process is simpler, but contact resistance increases and current flow decreases
Solution Approach 1:
The patent merges the connection structures of multiple stacked memory pillars into a shared common connection structure, where multiple pillars connect to a common interconnect rather than requiring individual connections. This merging approach reduces the number of contact points and interconnects needed, thereby reducing overall contact resistance while maintaining manufacturing simplicity.
Solution Approach 2:
The patent transitions from planar connections to three-dimensional stacked connections by vertically stacking memory pillars and using through-silicon vias (TSVs) to establish electrical connections between layers. This dimensional change allows for higher integration density while managing contact resistance through optimized vertical interconnect pathways.
2Productivity
If direct formation of upper-layer pillars is performed, then manufacturing process is faster, but lower-layer memory pillars are damaged
Solution Approach 1:
The patent applies a sacrificial layer on the surface of lower-layer memory pillars before forming upper-layer pillars. This preliminary protective action prevents damage to the lower-layer pillars during the formation process of upper-layer structures, ensuring manufacturing yield is maintained while enabling faster production through continuous processing.
Solution Approach 2:
The sacrificial layer acts as an intermediary protective element between the lower-layer memory pillars and the formation process of upper-layer pillars. This intermediary layer absorbs or mitigates potential damage during manufacturing, allowing the process to proceed without compromising the integrity of existing structures.
3Reliability
If more interconnects are added to connect stacked pillars, then electrical connection is improved, but device complexity increases
Solution Approach 1:
The patent combines multiple pillar connections into a common interconnect structure, where several memory pillars share a common electrical pathway. This merging reduces the total number of interconnects required compared to individual dedicated connections for each pillar, thereby reducing device complexity while maintaining adequate current flow through the shared connection.
Data Source
AI summary
According to one embodiment, a semiconductor memory includes: a first member extending in a first direction perpendicular to a surface of a substrate, and including a first semiconductor layer; first and second interconnects extending in a second direction parallel to the surface of the substrate, the second interconnect neighboring the first interconnect in a third direction; a second member extending in the first direction and above the first member, the second member including a second semiconductor layer; third and a fourth interconnects extending in the second direction, the fourth interconnect neighboring the third interconnect in the third direction; and a third semiconductor layer between the first and the second members, the third semiconductor layer being continuous with the first and the second semiconductor layers.