Stacked Memory Power Distribution via Master Die Segmentation
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Solution Overview
Problem
Conventional stacked memory devices experience a voltage drop in power supply due to longer power paths for upper semiconductor dies, leading to reduced power supply magnitude, which affects the operation of memory cells.
Innovation Solution
A stacked memory device architecture with a master semiconductor die and multiple slave dies, where the master die receives independent power supply voltages and distributes them to slave dies through through-silicon vias, with each slave die having separate power lines connected in parallel to maintain voltage stability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If power supply voltage is transferred from lower semiconductor die to upper semiconductor die through conventional paths, then power supply can reach all dies, but voltage drop occurs on longer paths causing reduced power magnitude
Solution Approach 1:
The patent segments the power supply architecture by providing independent power supply voltages (first and second power supply voltages) to the master semiconductor die, rather than transferring power sequentially through dies. This segmentation allows each die to receive power directly, eliminating the cumulative voltage drop that occurs in conventional sequential power transfer paths.
Solution Approach 2:
The master semiconductor die acts as an intermediary that receives multiple independent power supply voltages and distributes them to slave semiconductor dies through dedicated power lines. This intermediary role allows the master die to compensate for voltage drops by providing stable reference voltages to upper dies, ensuring reliable power supply without direct sequential transfer.
2Reliability
If multiple power supply voltages are provided to master semiconductor die independently, then voltage stability is improved across all dies, but device complexity increases
Solution Approach 1:
The patent merges the power distribution function into the master semiconductor die, which consolidates multiple power supply voltage inputs and distributes them to all slave dies. This merging approach simplifies the overall system architecture compared to providing independent power supplies to each die, as the master die serves as a centralized power distribution hub that manages voltage stability for the entire stack.
Data Source
AI summary
A stacked memory device includes a master semiconductor die and a plurality of slave semiconductor dies stacked on the master semiconductor die. The master semiconductor die includes a first power line coupled to a first power supply voltage, a second power line coupled to a second power supply voltage, a memory device coupled to the first power line, and a data input/output buffer coupled to the second power line. Each of the plurality of slave semiconductor dies includes third and fourth power lines and a memory device coupled to the third power line. The third power line is electrically connected to the first and fourth power lines, and the fourth power line is electrically disconnected from the second power line. The data input/output buffer buffers data communicated between an external device and the memory devices included in the master semiconductor die and the plurality of slave semiconductor dies.