Stacked Memory Re-timing Circuit Skew Alignment
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Solution Overview
Problem
Stacked memory devices face challenges in ensuring accurate signal transfer and timing alignment due to the complexity of three-dimensional chip stacking, particularly in direct access modes, where skew between command/address/data and clock/strobe signals can occur, affecting reliability.
Innovation Solution
Incorporating a re-timing circuit within the stacked memory device that receives input signals and clocks, performs re-timing operations based on a second clock, and outputs re-timed signals along with a replica clock to align and delay the first clock, ensuring precise signal transfer through through-electrodes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If signals are transferred through stacked semiconductor chips using through-electrodes, then integration degree and performance are improved, but signal skew and timing alignment issues occur
Solution Approach 1:
The re-timing circuit performs preliminary timing adjustment on input signals before they are transferred through the stacked chips. By latching input signals based on a second clock and outputting re-timed signals synchronized with a replica clock, the circuit proactively compensates for timing skew that would otherwise occur during signal transfer through the through-electrodes.
Solution Approach 2:
The re-timing circuit acts as an intermediary between the input signal source and the through-electrode transfer path. It receives input signals and clocks, performs re-timing operations, and outputs re-timed signals with a replica clock that accounts for delay time, thereby mediating the timing alignment between different signal paths in the stacked memory device.
2Reliability
If re-timing operation is performed to align signals, then signal transfer reliability is improved, but device complexity increases
Solution Approach 1:
The re-timing circuit performs multiple functions within a single integrated structure: it latches input signals, generates re-timed signals, produces a replica clock with reflected delay time, and synchronizes output signals. This multi-functionality achieves reliable signal transfer while minimizing the number of separate components needed.
Solution Approach 2:
The re-timing circuit changes the timing parameters of input signals by latching them based on a second clock and outputting re-timed signals synchronized with a replica clock that has reflected delay time. This parameter adjustment aligns signal timing without requiring complex external timing control circuits.
3Manufacturing precision
If multiple clocks are used for re-timing operation, then timing alignment precision is improved, but manufacturing complexity increases
Solution Approach 1:
The re-timing circuit generates the replica clock with reflected delay time in advance, before the actual signal transfer through the through-electrodes occurs. This preliminary clock generation ensures that timing alignment is already accounted for when signals are transferred, eliminating the need for complex post-transfer timing adjustments.
Solution Approach 2:
The re-timing circuit creates a replica clock that copies the timing characteristics of the first clock but with reflected delay time incorporated. This copied clock signal serves as a reference for synchronizing re-timed signals, achieving precise timing alignment without requiring multiple independent clock generation circuits.
Data Source
AI summary
A stacked memory device includes: a plurality of semiconductor chips that are stacked and transfer signals through a plurality of through-electrodes, wherein at least one of the semiconductor chips comprises: a re-timing circuit suitable for receiving input signals and first and second clocks, performing a re-timing operation of latching the input signals based on the second clock to output re-timed signals, and reflecting a delay time of the re-timing operation into the first clock to output a replica clock; and a transfer circuit suitable for transferring the re-timed signals to the through-electrodes based on the replica clock.