Stacked Memory Chip Redistributing Conductors to Reduce RC Delay
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Solution Overview
Problem
The manufacturing of high-density memory devices faces challenges due to the need for extensive interconnections between memory and peripheral circuits, leading to increased costs and potential limitations in memory bandwidth and power consumption, as existing technologies require many connections for bit lines, word lines, and other conductors, which can result in parasitic RC delays and higher power consumption.
Innovation Solution
A memory chip design with bit lines and word lines featuring redistribution conductors that minimize lateral signal travel distance, prioritizing connections for critical signals like common source lines first, followed by bit lines, and then word lines, to reduce parasitic delays and power consumption, while allowing for efficient stacking and modularization of memory and peripheral circuits.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If bonding pads are positioned away from memory circuit conductors to accommodate their larger size, then manufacturing is simplified, but lateral signal travel distance increases causing parasitic RC delays and higher power consumption
Solution Approach 1:
The patent transitions from planar interconnection to three-dimensional stacking, moving bonding pads vertically above conductors rather than laterally adjacent. This vertical arrangement in the stacked memory device eliminates the trade-off between bonding pad size and signal travel distance, as pads can be positioned directly above targets without lateral displacement.
Solution Approach 2:
The patent introduces via holes as intermediary conductive structures that vertically connect bonding pads to underlying memory circuit conductors. These via holes serve as mediators that eliminate the need for long lateral redistribution conductors, thereby reducing parasitic RC delays while accommodating large bonding pad sizes.
2Reliability
If numerous interconnections are provided for bit lines, word lines, and other conductors, then complete circuit functionality is achieved, but manufacturing complexity and cost increase
Solution Approach 1:
The patent employs three-dimensional stacking to vertically arrange multiple memory devices with their respective bonding pads. This vertical stacking consolidates numerous interconnections into a compact spatial arrangement, reducing manufacturing complexity while maintaining complete circuit functionality through the stacked configuration.
Solution Approach 2:
The patent divides the memory system into multiple discrete stacked devices, each handling specific interconnections. This segmentation allows complex interconnection requirements to be distributed across multiple simpler modular units, reducing the complexity of any single manufacturing process while achieving complete overall functionality.
3Ease of manufacture
If bonding pads are made larger to facilitate manufacturing, then ease of bonding is improved, but the lateral distance to memory circuit conductors increases causing parasitic RC delays
Solution Approach 1:
The patent resolves the contradiction between large bonding pad size and short signal travel distance by moving the interconnection from lateral (2D) to vertical (3D) arrangement. Bonding pads can be large for easy manufacturing while remaining directly above their target conductors via via holes, eliminating parasitic RC delays despite large pad dimensions.
Solution Approach 2:
Via holes serve as intermediary conductive elements that provide direct vertical electrical connection between large bonding pads and underlying memory circuit conductors. This intermediary structure allows large pads to be used for ease of manufacturing while maintaining short effective signal paths and low parasitic RC delays through the vertical via connection.
Data Source
AI summary
Roughly described, the invention involves a device including a memory chip having a memory array, bit lines in communication with data carrying nodes of the memory array, and word lines in communication with certain gate control nodes of the memory array. The memory chip has bonding pads formed on an interconnect surface at respective memory chip interconnect locations. Each of the bit lines and each of the word lines of the memory array includes a respective landing pad in a conductive layer of the chip, and these landing pads connected via redistribution conductors to respective ones of the set of memory chip bonding pads. The redistribution conductors for the bit lines have a positive average lateral signal travel distance which is less than that of the redistribution conductors for the word lines.