Stacked Body Memory Cell Refresh for Floating-Body Data Retention
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Solution Overview
Problem
Existing memory cells, such as DRAM, TTRAM, and dynamic flash memory cells, face issues with decreased operation margin and data retention performance due to changes in floating body channel voltage and discharge of positive holes, leading to reduced data retention.
Innovation Solution
A memory device with a structure comprising a semiconductor body, impurity regions, gate insulator layers, and gate conductor layers, where controlled voltages perform page erase, write, and read operations, including refresh operations to manage positive hole levels, enhancing data retention.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If a single MOS transistor memory cell is used to store data in the floating body channel, then the device complexity is reduced, but the data retention performance deteriorates due to discharge of positive holes and change in floating body channel voltage
Solution Approach 1:
The invention divides the memory cell into two separate MOS transistors instead of using a single transistor. Each transistor has its own floating body channel, and positive holes are stored in only one of them. This segmentation isolates the storage function from the control function, preventing voltage changes in the control transistor from affecting the stored data, thereby improving data retention while maintaining relatively simple device structure
Solution Approach 2:
The invention introduces an N+ layer that functions as both source/drain and electrical isolator. This intermediary layer separates the floating body channels of the two MOS transistors, preventing electrical interaction between them. The isolator ensures that voltage changes in one transistor do not couple to the other, protecting stored data from discharge while maintaining device simplicity
2Reliability
If refresh operations are performed to maintain data retention, then data retention performance is improved, but power consumption increases
Solution Approach 1:
The invention enables the memory cell to maintain its data state without requiring external refresh operations. By storing data in the floating body channel of one MOS transistor while the other serves as a control element, the design achieves stable data retention through its inherent structure. The isolated floating body channel naturally maintains stored positive holes without discharge, eliminating the need for power-consuming refresh cycles while maintaining high data retention performance
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution improves data retention and operation margin by managing positive hole levels through controlled voltage operations, increasing speed and reducing power consumption.
Implementation Method 1
a page write operation of increasing by an impact ionization phenomenon, the number of positive holes in the semiconductor body of a selected memory cell
Data Source
AI summary
A memory device includes pages arranged in a column direction and each constituted by memory cells arranged in a row direction on a substrate, each memory cell includes a semiconductor body, first and second impurity regions, and first and second gate conductor layers, the first and second impurity regions and first and second gate conductor layers are connected to source, bit, word, and plate lines respectively, and a page read operation includes a first refresh operation of increasing by an impact ionization phenomenon, a group of positive holes in the semiconductor body of a memory cell for which page writing has been performed and a subsequent second refresh operation of making some of a group of positive holes in the semiconductor body of a memory cell for which page writing has not been performed disappear and decreasing the number of positive holes.