3D Stacked Memory Structure With Sacrificial Layers for Lower Stress
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Solution Overview
Problem
The challenge in semiconductor manufacturing is to simplify the memory manufacturing process and improve yield while addressing increasing internal stress and difficulty as memory size shrinks, particularly for dynamic random access memory (DRAM) devices, which require faster response speed, lower power consumption, and higher storage density.
Innovation Solution
A method involving the formation of a stacked layer on a substrate with interlayer isolation layers and a sacrificial layer group, including a first, second, and third sacrificial layer, where these layers are selectively removed to form gaps and active pillars, and word lines, thereby simplifying the process and reducing internal stress, without the need for complex epitaxial growth or doping.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If the size of memory continues to shrink to achieve higher storage density, then storage density is improved, but the difficulty of manufacturing process and internal stress increase, reducing yield
Solution Approach 1:
The patent divides the memory structure into multiple stacked layers (first stacked layer, second stacked layer, third stacked layer) with each layer containing transistor structures and capacitor structures. This segmentation allows independent optimization of each layer's manufacturing process, reducing the cumulative difficulty and improving overall yield while achieving high storage density through vertical stacking.
Solution Approach 2:
The patent transitions from planar memory structures to three-dimensional stacked structures, arranging memory cells vertically in multiple layers above the substrate. This dimensional change enables higher storage density without further shrinking lateral dimensions, thereby avoiding the increased manufacturing difficulty and stress associated with continuous size reduction.
2Speed
If the size of memory continues to shrink to achieve faster response speed and lower power consumption, then performance is improved, but internal stress increases, reducing yield
Solution Approach 1:
The patent segments the memory device into multiple independent stacked layers, each with its own transistor and capacitor structures. This segmentation distributes internal stress across multiple layers rather than concentrating it in a single small structure, reducing the impact of stress on yield while maintaining the small feature sizes needed for fast response and low power consumption.
Solution Approach 2:
By moving to three-dimensional stacked architecture, the patent achieves performance improvement through vertical integration rather than lateral shrinking. This allows larger effective area for current flow (improving speed and reducing power) while the vertical stacking distributes mechanical stress, preventing yield reduction.
Data Source
AI summary
The present disclosure relates to a memory and a forming method thereof. The method of forming a memory includes: forming a stacked layer on a surface of a substrate, the stacked layer including interlayer isolation layers arranged at intervals in a first direction and a sacrificial layer group located between adjacent two of the interlayer isolation layers, the sacrificial layer group including a first sacrificial layer, a second sacrificial layer, and a third sacrificial layer sequentially stacked in the first direction, and the stacked layer including a transistor region, where the first direction is a direction perpendicular to a top surface of the substrate; removing the first sacrificial layer in the transistor region to form a first gap; forming an active pillar in the first gap; removing the second sacrificial layer and the third sacrificial layer in the transistor region to form a second gap.