3D Stacked Memory Device With Shared Wiring Layers
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Solution Overview
Problem
Current high-capacity nonvolatile memory devices, such as floating-gate NAND flash memories, face challenges in increasing integration density and manufacturing cost due to limitations in stacking memory cells and transistors without expanding the chip area.
Innovation Solution
A resistance random access memory device with two-terminal memory cells arranged in cross-point structures, where memory cells and transistors are stacked on a silicon substrate with shared wiring layers, allowing for increased integration density without expanding the transistor regions or peripheral circuit area.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If memory cells and transistors are stacked to increase integration density, then the degree of integration is improved, but the chip area expansion and manufacturing complexity increase
Solution Approach 1:
The patent transitions from planar arrangement to three-dimensional stacking, arranging memory cells and transistors in vertical layers. Multiple memory cell layers (first, second, third memory cell layers) are stacked above the substrate, with transistors positioned in between, enabling high integration density without expanding chip area.
Solution Approach 2:
The patent employs shared wiring structures where bit lines serve multiple functions: they connect to memory cells in different layers and also function as gate lines for transistors. The first bit lines connect to first memory cells and serve as gate lines for second transistors, reducing the number of separate wiring layers needed.
2Reliability
If more wiring layers are added to connect stacked memory cells and transistors, then connectivity is improved, but manufacturing steps and chip area increase
Solution Approach 1:
The patent implements multi-functional wiring where bit lines serve dual purposes: connecting memory cells vertically and acting as gate lines for transistors. First bit lines connect first memory cells to second memory cells and simultaneously serve as gate lines for second transistors, reducing the total number of wiring layers required.
Solution Approach 2:
The patent merges the function of separate bit lines and gate lines into a single wiring structure. The same conductive layer serves as both a bit line for memory cell access and a gate line for transistor control, consolidating multiple wiring functions into fewer physical layers.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables higher integration density of memory cells while maintaining a compact chip footprint and reducing manufacturing complexity and cost by using common steps for forming resistance change films and driver transistor components.
Implementation Method 1
a resistance change film (33) configured to change resistance in response to application of a voltage
Data Source
AI summary
A memory device according to an embodiment, includes a substrate, two or more resistance change memory cells stacked on the substrate, two or more transistors stacked on the substrate, and two or more wirings stacked on the substrate. One of the memory cells and one of the transistors are connected to each other via one of the wirings.