3D Stacked Memory Array Layout With Shared Wordlines and Bitlines
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Solution Overview
Problem
Existing semiconductor memory devices face challenges in achieving high integration density and multifunctionality due to limitations in connecting memory cells and components in a compact form.
Innovation Solution
The semiconductor memory device is designed with multiple semiconductor layers stacked vertically, where wordlines and bitlines are connected in the vertical direction, and sub-wordline drivers and sense amplifiers are integrated in a core peripheral layer, allowing for enhanced connectivity and increased integration density.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If memory cells are arranged in a matrix form in a single layer, then the device structure is simple, but the integration density is limited
Solution Approach 1:
The patent transitions from a two-dimensional planar arrangement to a three-dimensional stacked architecture by forming multiple semiconductor layers (first, second, and third layers) vertically. Memory cells are distributed across different layers, with wordlines and bitlines extending through multiple layers to access cells in different planes, thereby significantly increasing integration density while maintaining manageable structural complexity through systematic layering
Solution Approach 2:
The memory device is divided into multiple semiconductor layers, each containing sub-cell arrays. The first semiconductor layer includes first sub-cell arrays, the second layer includes second sub-cell arrays, and the third layer includes third sub-cell arrays. This segmentation allows independent optimization of each layer while collectively achieving high integration density
2Quantity of substance
If multiple semiconductor layers are stacked vertically to increase integration density, then more memory cells can be connected, but the connectivity complexity between layers increases
Solution Approach 1:
The wordlines and bitlines are designed to serve multiple functions across different layers. Wordlines extend from the first layer through the second layer to access memory cells in both layers, and similarly for bitlines. This multi-functional wiring approach reduces the need for separate dedicated connections for each layer, thereby managing connectivity complexity while accessing a larger number of memory cells
Solution Approach 2:
The patent merges the connectivity functions for multiple layers into shared wordline and bitline structures. Instead of providing separate independent connections for each memory cell layer, the same wordlines and bitlines are extended to access cells across multiple layers, reducing overall connectivity complexity while maintaining access to increased memory capacity
3Area of stationary object
If sub-wordline drivers and sense amplifiers are integrated in a core peripheral layer, then component sizes are maintained, but the manufacturing precision requirements increase
Solution Approach 1:
The device is segmented into distinct functional layers: memory cell layers (first and second semiconductor layers) and a core peripheral layer (third semiconductor layer) containing sub-wordline drivers and sense amplifiers. This segmentation allows independent optimization of each layer's manufacturing process and reduces the cumulative impact of alignment errors, as each layer can be processed and aligned independently with standardized interfaces
Data Source
AI summary
Provided is a semiconductor memory device including: a first layer including a first sub-cell array including memory cells; a second layer including a second sub-cell array; and a third layer including sub-wordline drivers and sense amplifiers, wherein the first, second, and third layers are stacked in a first direction perpendicular to the first layer, wherein the first layer includes first wordlines and first bitlines extending in the direction perpendicular to the first direction, wherein the second layer includes second wordlines and second bitlines extending in the direction perpendicular to the first direction, wherein the first wordlines are connected to the second wordlines in the first direction, wherein each of the first wordlines is connected to one of the sub-wordline drivers, wherein the first bitlines are connected to the second bitlines in the first direction, and wherein each of the first bitlines is connected to one of the sense amplifiers.