Stacked Semiconductor Memory Device Signal Path Optimization
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Solution Overview
Problem
In semiconductor memory devices with stacked chips, signal delay and increased power consumption occur due to long signal paths between master and slave chips, which worsen with more slave chips, limiting capacity and efficiency.
Innovation Solution
A semiconductor memory device design where a master integrated circuit chip is interposed between slave chips, featuring an interface unit for signal transfer and inter-chip interconnectors that reduce signal path length and transfer load, with external connectors for communication with external circuits.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If more slave chips are stacked to increase capacity, then the memory device capacity increases, but the signal path length increases causing signal delay and increased power consumption
Solution Approach 1:
The patent divides the stacked memory structure into multiple groups, with each group having its own master chip and slave chips. This segmentation allows signal paths to be contained within smaller groups rather than spanning the entire stack, reducing signal delay while maintaining high capacity through the combination of multiple groups.
Solution Approach 2:
The patent transitions from a single-column vertical stack to a multi-column three-dimensional structure. By arranging memory chips in multiple vertical columns and interconnecting them through lateral connections at intermediate levels, the signal path is redirected through additional spatial dimensions, reducing the vertical distance signals must travel and thereby reducing signal delay.
2Quantity of substance
If more slave chips are stacked to increase capacity, then the memory device capacity increases, but the power consumption increases due to longer signal paths
Solution Approach 1:
By segmenting the large stacked structure into smaller groups with local master chips, the patent reduces the distance over which signals must be transmitted. This segmentation decreases the total inter-chip connection length, thereby reducing power consumption while still achieving high overall capacity through the aggregation of multiple segments.
Solution Approach 2:
The patent introduces intermediate master chips that act as mediators between the top and bottom of the stack. These intermediary chips receive signals from external controllers and distribute them to slave chips in their local group, eliminating the need for signals to traverse the entire stack length, thus reducing power consumption.
3Quantity of substance
If slave chips are positioned farther from the master chip, then more chips can be stacked, but the signal path length increases
Solution Approach 1:
The patent utilizes three-dimensional space by creating multiple vertical columns and introducing lateral connections at intermediate levels. This allows slave chips positioned far vertically to be connected through lateral paths, effectively reducing the signal path length by utilizing horizontal dimensions rather than purely vertical connections.
Solution Approach 2:
By dividing the stack into multiple groups with local master chips positioned among the slave chips, the patent ensures that no slave chip is far from its local master. This segmentation strategy maintains short signal paths even as the total number of stacked chips increases, because each group operates semi-independently with localized signal paths.
Data Source
AI summary
A semiconductor memory device includes a memory structure including a first integrated circuit chip and a plurality of second integrated circuit chips stacked on each other, the first integrated circuit chip is interposed between a pair of the plurality of second integrated circuit chips, an interface unit disposed on the first integrated circuit chip, the memory structure is connected to a third circuit through the interface unit, and the interface unit transfers operation signals to the first integrated circuit chip and the plurality of second integrated circuit chips, at least one inter-chip interconnector connected with the interface unit and the first integrated circuit chip and the plurality of second integrated circuit chips, and an external interconnector connected with the interface unit and the third circuit.