Stacked Memory Test Circuit Using Segmented Modules and Compression
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Solution Overview
Problem
The existing methods for testing stacked memory devices face challenges in efficiently evaluating the circuits on read/write paths, data pads, write strobe pads, and read strobe pads, especially with the updated specifications like HBM 3.0, where it becomes difficult to test these components using the conventional methods.
Innovation Solution
The proposed solution involves a stacked memory device with specific circuits such as read/write circuits, test register circuits, data compression circuits, and timing control circuits that allow for separate testing of data pads, write strobe pads, and read strobe pads through various test modes, utilizing test input and output pads to generate and manipulate timing and strobe signals for effective evaluation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If conventional testing methods are used for stacked memory devices, then the testing process is simple, but it becomes difficult to test data pads, write strobe pads, and read strobe pads according to updated specifications like HBM 3.0
Solution Approach 1:
The test circuit is segmented into separate functional modules: a write circuit for writing test data through data pads, a read circuit for reading data, a test register circuit for data manipulation, and a data compression circuit for result compression. This segmentation allows each module to be independently configured and tested, enabling adaptation to updated specifications while maintaining manageable complexity through modular design.
Solution Approach 2:
The test circuit is designed with multi-functional capabilities to support both conventional testing and updated HBM 3.0 specifications. The same data pads, write strobe pads, and read strobe pads can be used for different test modes by configuring the test register circuit and data compression circuit appropriately, eliminating the need for separate dedicated test circuits for each specification version.
2Reliability
If separate testing of data pads, write strobe pads, and read strobe pads is implemented, then test coverage is improved, but test operation complexity increases
Solution Approach 1:
The testing process is divided into distinct operational phases: write phase where test data is written through data pads controlled by write strobe pads, and read phase where data is read back controlled by read strobe pads. The test register circuit separately handles data manipulation for each phase, allowing comprehensive test coverage while simplifying control through clear phase separation.
Solution Approach 2:
The read circuit reads back data that was written by the write circuit, creating a feedback loop. The data compression circuit then compresses this fed-back data to generate test results. This feedback mechanism enables verification of the complete write-read path, ensuring thorough test coverage while the automated compression reduces manual analysis complexity.
3Measurement precision
If comprehensive test circuits are added to test all pads and circuits, then test accuracy is improved, but manufacturing cost increases
Solution Approach 1:
The test circuits utilize the same data pads, write strobe pads, and read strobe pads that are used for normal memory operations, rather than requiring separate dedicated test pads. The test register circuit and data compression circuit are integrated into the existing memory controller structure, allowing comprehensive testing without adding significant external components, thereby maintaining manufacturing cost efficiency while achieving high test accuracy.
Solution Approach 2:
The memory device performs self-testing using its own internal circuits. The write circuit writes test data, the read circuit reads it back, and the data compression circuit processes the results—all within the device itself. This self-service approach eliminates the need for complex external test equipment, reducing overall system cost while maintaining high measurement precision through dedicated test functionality.
4Loss of substance
If data compression circuit is used to compress test data, then test output size is reduced, but circuit complexity increases
Solution Approach 1:
The data compression circuit is implemented as a separate functional module within the test circuit, distinct from the write and read circuits. This segmentation allows the compression function to be added without fundamentally redesigning the existing test architecture, reducing test data volume through dedicated compression logic while maintaining overall circuit modularity and manageable complexity.
Data Source
AI summary
A memory device includes a data pad; a read circuit outputting read or test data to the data pad according to a read timing signal and a read command; a write circuit receiving write data through the data pad according to a write timing signal; a test register circuit performing a preset operation on data and storing the data, and transferring the stored data as the test data in response to the read command, during a first test mode; a data compression circuit generating a test output signal by compressing the test data and outputting the test output signal to a first test output pad, during the first test mode; and a timing control circuit generating, according to first to third output control signals, the read timing signal and generating the write timing signal by delaying the read timing signal, during the first test mode.