Stacked Memory Die with TSVs for Fast FPGA Reconfiguration
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Solution Overview
Problem
Programmable integrated circuits face challenges in reconfiguration speed, energy consumption, and parallel reconfiguration capabilities, with traditional methods being several orders of magnitude slower than desired and costly in terms of silicon real estate and energy-intensive due to off-chip storage fetching.
Innovation Solution
The implementation of an integrated circuit package with in-package stacked memory elements and through-silicon vias (TSVs) allows for faster reconfiguration by storing configuration data closer to the logic sectors, reducing latency and energy consumption through local sector managers and secure device managers that manage and retrieve configuration bit streams efficiently.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If configuration data is stored in off-chip memory and fetched through the configuration circuit chain, then the programmable device can be reconfigured, but the reconfiguration speed is several orders of magnitude slower than desired
Solution Approach 1:
The patent transitions from a two-dimensional planar architecture to a three-dimensional stacked architecture by placing memory die directly over logic die through silicon interconnects. This vertical stacking reduces the physical distance configuration data must travel, enabling faster reconfiguration speeds and reducing latency by eliminating the need to fetch data through the entire configuration circuit chain from off-chip memory.
Solution Approach 2:
The patent introduces configuration data storage located in close proximity to the logic sectors as an intermediary between off-chip memory and the logic circuits. This intermediate storage layer acts as a buffer that holds pre-fetched configuration bit streams, allowing logic sectors to be reconfigured rapidly without repeatedly accessing off-chip memory through the slow configuration circuit chain.
2Quantity of substance
If off-chip storage is used to store configuration bit streams, then storage capacity is sufficient, but energy consumption increases due to repeated fetching
Solution Approach 1:
The patent implements pre-fetching of configuration bit streams into on-chip storage located near logic sectors before reconfiguration is needed. By preparing configuration data in advance and storing it in close proximity to the logic circuits, the system eliminates repeated energy-intensive fetching operations from off-chip memory during runtime reconfiguration events.
Solution Approach 2:
The patent introduces an intermediate configuration data storage layer positioned between off-chip memory and logic sectors. This intermediary storage reduces energy consumption by serving as a local cache that holds frequently accessed configuration bit streams, minimizing the need for repeated high-energy transfers from distant off-chip memory through the configuration circuit chain.
3Loss of time
If on-chip caching or buffering of pre-fetched configuration bit streams is implemented, then reconfiguration latency is reduced, but silicon real estate cost increases undesirably
Solution Approach 1:
The patent resolves the area-latency tradeoff by moving from a planar layout to a three-dimensional stacked architecture. Configuration data storage is placed in the vertical dimension directly over logic die through silicon interconnects, achieving fast reconfiguration latency without consuming additional lateral silicon real estate on the same die plane.
Solution Approach 2:
The patent divides the system into separate stacked layers: logic die containing logic sectors and a second die containing configuration data storage. This segmentation allows each layer to be optimized independently, with configuration storage positioned close to logic sectors through vertical interconnects, achieving low latency without increasing the footprint of either individual die.
4Device complexity
If traditional configuration circuit chain is used, then device complexity is manageable, but parallel reconfiguration capabilities are limited
Solution Approach 1:
The patent segments the configuration system into multiple independent logic sectors, each with its own local configuration data storage and reconfiguration circuitry. This segmentation enables parallel reconfiguration operations across different sectors without requiring a complex centralized configuration circuit chain, as each sector can be reconfigured independently through its own dedicated pathways.
Solution Approach 2:
The patent enables parallel reconfiguration by transitioning to a three-dimensional stacked architecture where multiple logic sectors on the logic die can simultaneously access configuration data from storage on the stacked memory die. This vertical arrangement provides multiple independent configuration pathways, allowing parallel reconfiguration capabilities without increasing the complexity of the configuration circuit chain.
Data Source
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AI summary
A system may include a host processor, a coprocessor for accelerating tasks received from the host processor, and one or more memory dies mounted to the coprocessor. The coprocessor and the memory die may be part of an integrated circuit package. The memory die may convey configuration bit streams to one or more logic sectors in programmable circuitry of the coprocessor over through-silicon vias. Each logic sector may include one or more data registers that are loaded with configuration data from the memory die. Multiple data registers may be loaded with configuration data simultaneously. The configuration data may be loaded onto an array of configuration memory cells using the data registers. Multiple data registers may be pipelined to allow simultaneous loading of configuration data into multiple sub-arrays of the array of configuration memory cells.