Stacked Memory Device Vertical Address Decoding
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Solution Overview
Problem
The integration density of multi-layered memory devices is limited due to difficulties in arranging circuits that support their operation, hindering the increase in operating speed and data processing capabilities required for compact semiconductor products.
Innovation Solution
A stacked memory device with multiple memory layers, each containing an array of memory cells, utilizes a first active circuit unit for processing vertical and horizontal address information and generating selection signals, and a second active circuit unit for managing memory layers, including main decoders and sense amplifiers, to enhance access efficiency and integration density.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If multi-layered memory device structure is adopted to increase integration density, then memory capacity is improved, but circuit arrangement difficulty increases
Solution Approach 1:
The memory device is divided into multiple stacked memory layers, with each layer containing a portion of the memory cells. This segmentation allows the large-scale memory array to be distributed across three-dimensional space, increasing capacity while managing circuit complexity through modular organization of decoders and circuit units at different vertical levels.
Solution Approach 2:
The patent transitions from a planar two-dimensional memory layout to a three-dimensional stacked architecture. Memory layers are arranged vertically along the z-axis, with decoders and circuit units positioned at different heights. This dimensional change enables significant capacity expansion without proportionally increasing the footprint area, while circuit arrangements are optimized for the vertical stacking geometry.
2Speed
If more memory layers are stacked to increase integration density, then operating speed may be improved, but circuit arrangement becomes more difficult
Solution Approach 1:
The decoder functionality is segmented across multiple vertical levels. First decoders are positioned at intermediate heights between memory layers, while second decoders are located at different vertical positions. This segmentation allows address decoding to be distributed throughout the stack, reducing signal propagation distances and enabling faster access times while managing the complexity of inter-layer circuit connections.
Solution Approach 2:
The patent introduces intermediate circuit units and decoder stages positioned between memory layers to facilitate signal routing and processing. These intermediary components act as mediators that manage data flow between the stacked memory layers and external interfaces, enabling high-speed operation while organizing the complex circuit arrangements in a structured manner.
Data Source
AI summary
A stacked memory device includes a plurality of memory layers, where at least one of the plurality of memory layers is stacked on another of the plurality of memory layers and each of the memory layers includes an array of memory cells, a first active circuit unit configured to classify and process address information for at least one of the memory cells as vertical address information and horizontal address information, and at least one second active circuit unit configured to generate a memory selection signal for at least one of the memory cells based on signals processed by the first active circuit unit.