Stacked Memory Device Vertical Interconnect Architecture
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Solution Overview
Problem
The integration of semiconductor memory devices is limited by the need for extensive horizontal connections between memory units and peripheral circuits, which restricts the improvement of memory device integrity and increases complexity in line connections.
Innovation Solution
A stacked memory device design where peripheral circuits are formed above or below memory units, eliminating the need for horizontal connections and allowing for a more compact and efficient layout by using string selection pads and bit lines, thereby simplifying the line connection between memory and peripheral circuits.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of operation
If peripheral circuits are arranged horizontally adjacent to memory units, then ease of connection is improved, but device complexity and area increase
Solution Approach 1:
The patent transitions from a planar horizontal arrangement to a three-dimensional stacked arrangement where peripheral circuits are positioned vertically above or below memory units. This dimensional change eliminates the need for extensive horizontal interconnect lines, thereby reducing line connection complexity while maintaining ease of connection through vertical stacking.
Solution Approach 2:
The patent merges the memory units and peripheral circuits into a single stacked structure, combining previously separate horizontal components into an integrated vertical assembly. This merging reduces the overall device area and simplifies the interconnection architecture by eliminating long horizontal traces.
2Ease of manufacture
If horizontal connections are used between memory and peripheral circuits, then ease of manufacturing is improved, but memory device integrity deteriorates
Solution Approach 1:
The patent employs vertical stacking in the third dimension to replace horizontal connections. This approach maintains manufacturing feasibility through standard semiconductor fabrication processes while improving memory device integrity by reducing the length and complexity of interconnect paths, thereby minimizing signal degradation and interference.
3Adaptability or versatility
If extensive horizontal connections are used, then connectivity is improved, but device area increases
Solution Approach 1:
The patent utilizes vertical stacking to achieve full connectivity between memory units and peripheral circuits without requiring extensive horizontal space. By moving connections into the vertical dimension, the device maintains comprehensive connectivity while dramatically reducing the planar footprint and overall device area.
Data Source
AI summary
A stacked memory device may include at least one memory unit and at least one peripheral circuit unit arranged either above or below the at least one memory unit. The at least one memory unit may include a memory string array, a plurality of bit lines, and a plurality of string selection pads. The memory string may include a plurality of memory strings arranged in a matrix and each of the memory strings may include a plurality of memory cells and a string selection device arranged perpendicular to a substrate. The plurality of bit lines may extend in a first direction and may be connected to ends of the plurality of memory strings. The plurality of string selection pads may be arrayed in a single line along the first direction and may be connected to the string selection devices included in the plurality of memory strings.