Stacked Memory Array Through-Via Sharing for Dense Stable NAND
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Solution Overview
Problem
The integration of semiconductor devices is limited by the area occupied by unit memory cells, and there is a need for improved operational reliability and stability in three-dimensional semiconductor structures.
Innovation Solution
A semiconductor device is designed with stacked memory cells in a three-dimensional configuration, incorporating interconnection structures and a row decoder to connect and control multiple memory layers, reducing the area occupied by peripheral circuits and enhancing reliability through shared access and control mechanisms.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If memory cells are arranged in a single layer on a substrate, then the structure is simple and manufacturing is easier, but the degree of integration reaches a limit and area efficiency is low
Solution Approach 1:
The patent transitions from a two-dimensional single-layer memory cell arrangement to a three-dimensional stacked configuration. Multiple memory cell layers are vertically stacked on the substrate, with each layer containing memory strings and associated word lines. This dimensional change enables significantly higher storage capacity per unit area while maintaining manufacturability through standardized layer-by-layer fabrication processes.
2Productivity
If multiple memory cell arrays are stacked in three dimensions, then the degree of integration improves, but the area occupied by peripheral circuits increases and operational reliability becomes more challenging
Solution Approach 1:
The patent implements shared peripheral circuits that serve multiple stacked memory cell arrays. A single page buffer can selectively access memory strings from different memory cell layers through the first interconnection structure, and a single row decoder can control word lines across multiple layers through the second interconnection structure. This multi-functional design allows peripheral circuits to manage data operations for several memory arrays simultaneously, dramatically reducing the total area required for peripheral support infrastructure.
3Productivity
If multiple memory cell arrays are stacked in three dimensions, then the degree of integration improves, but operational reliability and stability become more challenging
Solution Approach 1:
The patent divides the three-dimensional memory structure into distinct, independently addressable memory cell layers, each with its own set of memory strings and word lines. The first memory cell array and second memory cell array are segmented as separate functional units that can be independently accessed and controlled. This segmentation allows for modular operation where faults in one layer do not necessarily affect others, and enables targeted repair or replacement strategies that preserve overall system reliability.
Data Source
AI summary
A semiconductor device may include a first memory cell array including a first source line, a first bit line, a first memory string, and first word lines; a second memory cell array including a second source line, a second bit line, a second memory string, and second word lines; a first interconnection structure including a first through via passing through the first memory cell array and commonly connected to the first bit line and the second bit line; a second interconnection structure including a second through via passing through the first memory cell array and commonly connected to the first word line and the second word line; a page buffer selectively accessing the first memory string or the second memory string through the first interconnection structure; and a row decoder commonly controlling the first word line and the second word line through the second interconnection structure.