Stacked Memory Wafer Layout for Row Decoder and Page Buffer Separation
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Solution Overview
Problem
The challenge is to enhance the layout utilization efficiency and reduce the size of memory devices with increasing integration and operating speed, while minimizing the occupation area of row decoders and page buffer circuits, and addressing the limitations in disposing peripheral circuits due to the presence of page buffer circuits.
Innovation Solution
The solution involves stacking and bonding two wafers, with the first wafer containing a memory cell array and a logic structure including a page buffer circuit, and the second wafer containing a logic structure with a row decoder and peripheral circuit, allowing for improved layout efficiency and separate placement of peripheral circuits to avoid limitations imposed by the page buffer circuit.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If page buffer circuits are disposed on the same wafer as memory cell arrays, then integration is achieved, but layout utilization efficiency is reduced and device size increases
Solution Approach 1:
The memory device is divided into two separate wafers: a first wafer containing the memory cell array and a second wafer containing the page buffer circuit. This segmentation allows each component to be optimized independently and reduces the layout area required on a single wafer, thereby improving layout utilization efficiency while maintaining integration through wafer bonding.
2Device complexity
If row decoders and page buffer circuits share the same wafer, then device complexity is reduced, but the occupation area increases
Solution Approach 1:
The patent transitions from a two-dimensional layout on a single wafer to a three-dimensional stacked architecture using wafer bonding. By moving the page buffer circuit to a separate wafer and bonding it to the first wafer, the device utilizes the vertical dimension, thereby reducing the occupation area on each individual wafer while maintaining circuit integration.
3Ease of manufacture
If peripheral circuits are disposed on the same wafer as memory cell arrays, then manufacturing steps are simplified, but functional errors due to heat increase
Solution Approach 1:
The memory device is segmented into two separate wafers with distinct thermal characteristics. The first wafer contains the memory cell array and the second wafer contains the peripheral circuits including row decoders and page buffer circuits. This segmentation allows heat generated by peripheral circuits to be isolated from the memory cell array, reducing thermal interference and functional errors while still enabling integrated manufacturing through wafer bonding.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration enhances layout utilization efficiency, reduces the size of memory devices, and minimizes the occurrence of functional errors due to heat during the manufacturing process, while simplifying the manufacturing steps and reducing costs.
Implementation Method 1
a first wafer, and a second wafer stacked on and bonded to the first wafer
Data Source
AI summary
A memory may include a first wafer, and a second wafer stacked on and bonded to the first wafer. The first wafer may include a cell structure including a memory cell array; and a first logic structure disposed under the cell structure, and including a row control circuit. The second wafer may include a second logic structure including a column control circuit.