Stacked MiM Capacitor Design for High Density ICs
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Solution Overview
Problem
The challenge in semiconductor manufacturing is to minimize the physical area occupied by capacitors on integrated circuits (ICs) while maintaining high capacitance and reliability, as thinner dielectric layers are more challenging to control and tend to conduct more current, affecting voltage and thermal stability.
Innovation Solution
A stacked capacitor design is implemented, where two Metal-Insulator-Metal (MiM) capacitors are connected in parallel with stress-relieving slots and vias, allowing the same mask to be used for patterning, reducing the number of masks required and minimizing area loss, and ensuring thermal stability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If the dielectric layer is made thinner to maximise capacitance, then the capacitance value increases, but the thickness control becomes more challenging and reliability decreases
Solution Approach 1:
The patent transitions from a planar capacitor design to a three-dimensional stacked capacitor structure. By stacking multiple capacitor units vertically, the effective capacitance is increased without requiring thinner dielectric layers. Each stack unit maintains a practical dielectric thickness while the cumulative capacitance of multiple stacks in parallel achieves the desired high capacitance value, thus avoiding the manufacturing precision issues associated with ultra-thin dielectric layers.
2Quantity of substance
If the dielectric layer is made thinner to maximise capacitance, then the capacitance value increases, but the reliability and voltage stability deteriorate due to higher electric fields
Solution Approach 1:
By stacking multiple capacitor units vertically rather than using a single thin dielectric layer, the electric field is distributed across multiple thicker dielectric layers. Each dielectric layer operates within safe electric field limits, preventing breakdown while achieving high total capacitance through the parallel combination of multiple stacks.
3Reliability
If large metal areas are used for capacitor plates to reduce parasitic resistance, then the conductivity improves, but the thermal stress and mechanical stability worsen
Solution Approach 1:
The capacitor plates are segmented into multiple smaller metal regions arranged in a stacked configuration. Each metal region is connected through vertical vias, creating a distributed network that maintains low parasitic resistance while limiting the thermal stress in any single metal area. This segmentation prevents excessive stress accumulation that would occur with large continuous metal areas.
Solution Approach 2:
The patent distributes the capacitor plate area across multiple vertical levels rather than concentrating it in a single large planar area. The stacked structure with vias connecting metal layers at different heights creates multiple conduction paths, reducing parasitic resistance while the distributed layout reduces thermal stress concentration.
4Stability of the object's composition
If a matrix of small cells is used to solve thermal expansion issues, then the thermal stability improves, but the overall capacitor area increases
Solution Approach 1:
The patent resolves the thermal stability issue by stacking capacitor units vertically in the third dimension rather than expanding the cell matrix horizontally. Multiple capacitor units share common metal plates and are connected through vias, achieving the required capacitance value without increasing the planar footprint. This vertical stacking maintains thermal stability while minimizing the overall capacitor area.
Data Source
AI summary
A device comprises a substrate (22); a first MiM capacitor (10,20,11) disposed over the substrate; and a second MiM capacitor (10′,20′,11) disposed over the first MiM capacitor. The first MiM capacitor and the second MiM capacitor are electrically connected in parallel. The two MiM capacitors are vertically stacked one above the other.Each MiM capacitor comprises an interconnection layer (10,10′) of the CMOS process as one plate and a thinner conductive layer (11,11′) as the second plate, with an insulating layer (20,20′) disposed therebetween. This allows each MiM capacitor to be formed between two CMOS process interconnection layers.The second plate of the second MiM capacitor is substantially co-extensive with the second plate of the first MiM capacitor, and is disposed substantially directly over the second plate of the first MiM capacitor. The same mask may be used to pattern the second plate of the second MiM capacitor and the second plate of the first MiM capacitor. This minimizes the number of masks required, and so minimizes the mask investment cost.