Stacked Semiconductor Module Layout for Warpage Suppression
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Solution Overview
Problem
Existing semiconductor packages face warpage issues due to accumulated shrinkage stresses from molding compounds, which are exacerbated by stacking multiple chips, increasing manufacturing complexity and cost.
Innovation Solution
A semiconductor module design where chips are stacked with overlapping areas to disperse shrinkage stress by positioning them diagonally and using a reference panel with a mold portion to minimize overlapping areas between stacked chips, reducing warpage before singulation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If multiple chips are stacked to increase capacity, then storage capacity is improved, but warpage occurs due to accumulated shrinkage stresses
Solution Approach 1:
The patent applies asymmetry by intentionally designing offset positions between stacked chips rather than aligning them perfectly. The second chip is positioned at an offset position relative to the first chip, creating an asymmetric stacking structure that reduces the accumulation of shrinkage stresses and suppresses warpage while maintaining increased storage capacity through 3D stacking
2Stability of the object's composition
If metal layer is added to suppress warpage, then warpage control is improved, but manufacturing complexity and cost increase
Solution Approach 1:
The patent extracts and removes the metal layer from the package structure, replacing it with an offset chip stacking arrangement. This eliminates the need for additional metal layers while maintaining warpage suppression through the asymmetric positioning of chips, thereby reducing manufacturing complexity and cost
3Speed
If chips are aligned perfectly in stacking direction, then connection efficiency is improved, but shrinkage stress concentrates causing warpage
Solution Approach 1:
The patent resolves this contradiction by introducing asymmetric offset positioning between stacked chips. The second chip is deliberately positioned at an offset position rather than perfectly aligned with the first chip, which disperses shrinkage stress concentration while maintaining adequate connection efficiency through controlled offset distances that preserve electrical connection pathways
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The design effectively suppresses warpage in the semiconductor module, facilitating easy singulation and reducing manufacturing complexity and cost by dispersing shrinkage stress through strategic chip placement and mold portion overlap reduction.
Implementation Method 1
when shrinkage stresses of the first molding compound and the second molding compound accumulate, warpage may occur
Data Source
AI summary
A semiconductor module includes: a reference panel, which includes a plurality of reference chips arranged in a row and a reference molded section that fills at least spaces between the plurality of reference chips; and a layered panel which comprises layered chips layered respectively onto the reference chips, and a layered molded section that fills at least spaces between the plurality of layered chips, the layered panel being layered onto one side of the reference panel. Each of the layered chips is disposed so that a partial region thereof overlaps with a partial region of the respective reference chip in a layering direction and is disposed so as to overlap with the reference molded section. The reference chips are disposed so as to overlap with the layered molded section.