Stacked Multi-Vt FET Gate Structure for Speed-Leakage Tradeoffs
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Solution Overview
Problem
Existing semiconductor technologies face challenges in producing multi-threshold voltage (Vt) field effect transistors (FETs) that are compatible with advanced nodes, as they struggle to maintain thermal budgets and provide both shared and independent gates with effective metal gate patterning and dipole patterning.
Innovation Solution
The development of semiconductor structures featuring stacked FETs with multi-Vt replacement metal gates, where different work function metals and nanosheet stacks are used to create distinct threshold voltages, and backside power delivery networks are integrated to enhance thermal budgets and gate stack performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If FETs with lower Vts are used, then switching speed is improved, but power leakage increases
Solution Approach 1:
The gate is segmented into multiple independent gates with different work function metals, allowing each gate to control different channels with different threshold voltages. This enables simultaneous optimization of switching speed and power leakage by assigning lower Vt gates to time-critical paths and higher Vt gates to non-time-critical paths within the same device structure.
Solution Approach 2:
Different regions of the gate structure are assigned different work function metals to create locally optimized threshold voltages. The first gate uses a first work function metal for one set of channels, while the second gate uses a second work function metal for another set of channels, allowing each region to have the optimal Vt for its specific function.
2Loss of energy
If FETs with higher Vts are used, then power leakage is reduced, but switching speed decreases
Solution Approach 1:
The gate is segmented into multiple independent gates with different work function metals, allowing each gate to control different channels with different threshold voltages. This enables simultaneous optimization of switching speed and power leakage by assigning lower Vt gates to time-critical paths and higher Vt gates to non-time-critical paths within the same device structure.
Solution Approach 2:
Different regions of the gate structure are assigned different work function metals to create locally optimized threshold voltages. The first gate uses a first work function metal for one set of channels, while the second gate uses a second work function metal for another set of channels, allowing each region to have the optimal Vt for its specific function.
3Temperature
If replacement metal gate structures are implemented, then thermal budget is improved, but manufacturing complexity increases
Solution Approach 1:
The gate structure is divided into multiple replaceable metal gate segments, each with its own work function metal layer. This segmentation allows for improved thermal budget control during fabrication while the modular nature of the segmented gates actually simplifies the overall manufacturing process by enabling independent optimization of each gate segment.
Solution Approach 2:
The replacement metal gate structure serves multiple functions: it provides improved thermal budget compatibility, enables multi-Vt operation, and maintains compatibility with existing fabrication processes. The universal gate structure can accommodate different work function metals without requiring fundamental process changes.
Data Source
AI summary
A semiconductor structure is presented including a first field effect transistor (FET), the first FET including at least a first set of fins and a second set of fins, the first set of fins surrounded by a first work function metal (WFM) and the second set of fins surrounded by a second WFM and a second FET formed directly over the first FET, the second FET including at least a first nanosheet stack and a second nanosheet stack, the first nanosheet stack surrounded by a third WFM and the second nanosheet stack surrounded by a third WFM with dipoles. The semiconductor structure further includes first contacts disposed from the first and second WFMs of the first FET to back-end-of-line (BEOL) components and second contacts disposed from a backside power delivery network (BSPDN) through the third WFM of the second FET to a top surface of the first and second WFMs of the first FET.