Stacked Multi-Chip Thermal Dissipation via Segmented TSV
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Solution Overview
Problem
Conventional stacked multi-chips using TSV technology face challenges with inadequate thermal dissipation, difficulty in constructing fully-stacked TSV for all chips, and positioning voltage level shifters.
Innovation Solution
A stacked multi-chip design featuring a base layer with a mounting panel and redistributed layer, where each chip includes an electrically non-conductive layer with TSV channels for thermal conductivity and connective layers for easy stacking and voltage level shifter alignment, facilitating efficient thermal dissipation and construction of fully-stacked TSV.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If conventional TSV technology is used to stack chips for high density and smaller dimensions, then speed and power performance are improved, but thermal dissipation becomes inadequate
Solution Approach 1:
The patent divides the thermal management function from the electrical interconnection function by introducing separate thermal vias alongside the electrical TSVs. This segmentation allows independent optimization of thermal conduction paths without interfering with electrical signal integrity, resolving the contradiction between high-speed electrical performance and thermal dissipation.
Solution Approach 2:
The patent introduces thermal vias as intermediary structures that specifically handle heat transfer between stacked chips. These thermal vias act as mediators between the heat-generating components and the heat sink, providing a dedicated thermal conduction path that does not interfere with the electrical TSV functionality, thus improving thermal dissipation while maintaining electrical performance.
2Volume of moving object
If conventional TSV stacking is used to achieve high density interconnections, then device miniaturization is achieved, but construction of fully-stacked TSV for all chips becomes difficult
Solution Approach 1:
The patent segments the via structures into electrical TSVs and thermal vias with different functional requirements. This segmentation allows simplified construction processes where thermal vias can be formed with less stringent alignment tolerances compared to electrical TSVs, making the overall stacking process more manufacturable while maintaining compact dimensions.
Solution Approach 2:
The patent applies different quality requirements to different via types: electrical TSVs require precise alignment and insulation for high-speed signaling, while thermal vias can have relaxed alignment tolerances since they only need to conduct heat. This local quality differentiation simplifies the overall manufacturing process by allowing less precise fabrication for the thermal conduction paths.
3Quantity of substance
If conventional stacked multi-chip design is used, then high density interconnection is achieved, but positioning of voltage level shifters becomes difficult
Solution Approach 1:
The patent resolves the positioning difficulty by transitioning from two-dimensional planar positioning to three-dimensional vertical stacking. Voltage level shifters are positioned in the vertical dimension between chip stacks, utilizing the Z-axis space that is otherwise unused. This dimensional transition allows high-density interconnections in the XY plane while providing accessible positions for voltage level shifters in the vertical direction.
Solution Approach 2:
The patent introduces intermediary structures such as redistribution layers and via structures that serve dual purposes: maintaining high-density interconnections while providing designated positions for voltage level shifters. These intermediary elements act as mediators that reconcile the conflicting requirements of density and positioning ease.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The design enhances thermal dissipation, simplifies the construction of fully-stacked TSV, and allows for easy positioning of voltage level shifters, improving performance and ease of assembly in high-density electrical interconnections.
Implementation Method 1
The electrically non-conductive layer comprises a TSV channel
Data Source
AI summary
A stacked multi-chip comprises a base layer, a first chip, a first stacked chip and at least one second stacked chip. The base layer comprises a mounting panel and a redistributed layer. The redistributed layer is mounted on the mounting panel. The first chip comprises an electrically non-conductive layer and a connective layer. The electrically non-conductive layer comprises a TSV channel. The connective layer abuts the redistributed layer. The first stacked chip is mounted on the first chip and comprises an electrically non-conductive layer and a connective layer. The electrically non-conductive layer comprises a TSV channel that is connected to the TSV channel of the first chip. The second stacked chip is mounted on the first stacked chip and comprises an electrically non-conductive layer and a connective layer. The electrically non-conductive layer comprises a TSV channel. The connective layer is connected to the connective layer of the first stacked chip.