Stacked Multi-Gate Semiconductor Layout With Backside Contacts
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Solution Overview
Problem
Existing semiconductor devices face challenges in integrating stacked multi-gate transistors effectively, leading to inefficiencies in device density and current control, while also struggling with short channel effects.
Innovation Solution
A semiconductor device design featuring a substrate with sequentially stacked active patterns and gate electrodes, along with source/drain patterns and backside contacts, allows for improved integration and electrical connectivity through a complex network of gate and source/drain structures.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If stacked multi-gate transistors are implemented to increase device density, then integration is improved, but manufacturing complexity increases
Solution Approach 1:
The patent divides the transistor structure into multiple independent multi-gate transistors stacked vertically, with each transistor having its own gate electrode, source/drain regions, and contact patterns. This segmentation allows independent optimization of each transistor while achieving high overall device density through vertical stacking.
Solution Approach 2:
The patent transitions from planar transistor arrangement to three-dimensional vertical stacking, utilizing the vertical dimension to increase device density. Multiple multi-gate transistors are stacked one on top of another, effectively adding a third dimension to the device architecture.
2Reliability
If gate length is increased to improve current control, then current control capability is enhanced, but device density decreases
Solution Approach 1:
The patent compensates for reduced gate length by utilizing vertical stacking in the third dimension. Multiple gate electrodes are stacked vertically, providing sufficient gate control area and current control capability even when individual gate lengths are reduced, thus maintaining device density.
Solution Approach 2:
The patent employs different gate electrode configurations for different transistors in the stack, optimizing each gate's local characteristics. Some gates may have different lengths, widths, or materials tailored to their specific functional requirements, allowing optimal current control without uniform increase in gate length across all transistors.
3Reliability
If short channel effects are suppressed by increasing gate length, then SCE is reduced, but device density decreases
Solution Approach 1:
The patent suppresses short channel effects by distributing the gate control across multiple vertically stacked gate electrodes. Each gate electrode provides independent control over its corresponding channel, and the cumulative effect of multiple gates provides sufficient control to suppress SCE even with reduced individual gate lengths.
Solution Approach 2:
The patent combines multiple gate electrodes and their respective control regions into a unified stacked structure. The combined control capability of multiple gates working in sequence or parallel provides sufficient control to suppress short channel effects, effectively merging the control functions of individual gates into a collective system.
Data Source
AI summary
A semiconductor device may include a substrate; a first active pattern and a second active pattern sequentially stacked on the first substrate, a first gate electrode and a second gate electrode intersecting the first active pattern and the second active pattern, respectively; a first-level source/drain pattern on a sidewall of the first gate electrode and connected to the first active pattern; a second-level source/drain pattern on a sidewall of the second gate electrode and connected to the second active pattern; a first backside source/drain contact penetrating the substrate and connected to the first-level source/drain pattern; a second backside source/drain contact penetrating the substrate and connected to the second-level source/drain pattern; a connection wiring pattern connecting the first backside source/drain contact and the second backside source/drain contact; and a backside gate contact penetrating the substrate and connected to the first gate electrode and the second gate electrode.