Stacked NAND Resistive Memory Cell Strings for Integration Density
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Solution Overview
Problem
Conventional resistive memory devices, such as RRAM and phase change memory devices, face limitations in device integration and efficiency due to their NAND-type cell unit configurations, which restrict improvements in reliability and programming efficiency.
Innovation Solution
A NAND-type resistive memory cell string is designed with a bit line and serially connected resistive memory cells, including heater elements and variable resistors, along with switching devices, allowing for improved integration and programming efficiency by stacking cells in an insulating layer on a semiconductor substrate.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If NAND-type cell units are used in resistive memory devices, then device integration is improved, but programming efficiency and reliability remain limited
Solution Approach 1:
The patent transitions from planar 2D cell arrangements to vertical 3D stacked configurations. Multiple resistive memory cells are stacked along the vertical dimension, with bit lines and word lines extending through multiple layers. This dimensional change enables higher integration density while maintaining reliable programming through improved cell isolation and controlled current paths in the vertical stacking architecture.
2Area of stationary object
If multiple variable resistive devices are serially connected in NAND-type cell units, then integration density increases, but control over resistance states becomes more difficult
Solution Approach 1:
The patent segments the control mechanism into distinct bit lines and word lines that independently address specific cells within the stacked array. Each cell can be selectively accessed by activating appropriate combinations of bit and word lines, enabling precise control over individual resistance states even when multiple cells are serially connected in vertical stacks. This segmentation prevents interference between adjacent cells during programming operations.
3Productivity
If phase change memory cells are stacked with shared bit lines, then device integration is enhanced, but programming efficiency is reduced
Solution Approach 1:
The patent introduces switching devices as intermediary elements between the bit lines/word lines and the variable resistive devices in each stacked cell. These switching devices act as mediators that enable selective activation of individual cells or groups of cells, allowing efficient programming by directing current only through targeted cells rather than requiring simultaneous programming of all stacked cells. This intermediary control mechanism preserves programming speed while achieving high integration through vertical stacking.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration enhances the integration density and programming efficiency of resistive memory devices, enabling better control over resistance states and improved data storage capabilities.
Implementation Method 1
a heater element connected between the first node and the second node
Data Source
AI summary
A non-volatile memory device includes a substrate, an insulating layer on the substrate, and a plurality of serially connected resistive memory cells stacked in the insulating layer such that a first one of the plurality of resistive memory cells is on the substrate and a next one of the plurality of resistive memory cells is on the first one of the plurality of resistive memory cells to define a NAND-type resistive memory cell string. A bit line on the insulating layer is electrically connected to a last one of the plurality of resistive memory cells. At least one of the plurality of resistive memory cells may include a switching device and a data storage element including a variable resistor connected in parallel with the switching device. Related devices and fabrication methods are also discussed.