Stacked NAND Memory Layout With Shared Gates for Higher Bit Density
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Solution Overview
Problem
The rapid scaling of NAND flash memories faces challenges such as limitations in lithography techniques, worsening short-channel and narrow-channel effects, and increased statistical variations in dopant impurities, making it difficult to further increase bit density through simple scaling.
Innovation Solution
A stacked semiconductor memory structure where multiple active areas are formed perpendicular to the substrate, sharing gate electrodes, allowing for increased bit density without relying heavily on advanced lithography techniques, and incorporating layer selection gate transistors to maintain compatibility with conventional flash memory designs.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If simple scaling of element size in horizontal plane is used to increase bit density, then manufacturing cost per bit is reduced, but lithography technique limitations and short-channel effects worsen
Solution Approach 1:
The patent transitions from two-dimensional planar scaling to three-dimensional stacked architecture. Multiple memory layers are stacked vertically with shared gate electrodes, enabling bit density increase along the vertical dimension while maintaining horizontal feature sizes that avoid severe short-channel effects and lithography limitations.
Solution Approach 2:
Multiple active areas across different layers share common gate electrodes. This merging of gate structures reduces the total number of lithography steps required, as gate patterns are formed once and serve multiple layers simultaneously, while still achieving high bit density through vertical stacking.
2Quantity of substance
If number of memory layers is increased to increase bit density, then bit density is improved, but number of manufacturing steps largely increases
Solution Approach 1:
Multiple memory layers share common gate electrodes and use simultaneous patterning techniques. Instead of forming gates layer-by-layer, the structure uses merged gate regions that can be patterned in a single lithography step, reducing manufacturing complexity despite having multiple stacked layers.
Solution Approach 2:
The shared gate electrodes serve multiple active areas across different layers simultaneously. This multi-functional gate structure eliminates the need for separate gate formation processes for each layer, significantly reducing the number of manufacturing steps while maintaining high bit density.
3Quantity of substance
If element dimensions are decreased to increase bit density, then bit density is improved, but short-channel effect and narrow-channel effect abruptly worsen
Solution Approach 1:
The patent moves the scaling challenge from the horizontal plane to the vertical dimension. By stacking memory layers vertically, bit density increases without requiring further reduction of horizontal feature sizes, thereby avoiding the exacerbation of short-channel and narrow-channel effects that occur with continued planar scaling.
Data Source
AI summary
A semiconductor memory includes a plurality of stripe-like active areas formed by stacking, in a direction perpendicular to a substrate, a plurality of layers extending parallel to the substrate, a first gate electrode formed on first side surfaces of the active areas, the first side surfaces being perpendicular to the substrate, a second gate electrode formed on second side surfaces of the active areas, the second side surfaces being perpendicular to the substrate. The layers are patterned in self-alignment with each other, intersections of the active areas and the first gate electrode form a plurality of memory cells, and the plurality of memory cells in an intersecting plane share the first gate electrode.