Stacked Nanosheet Gate Structure for Source/Drain Overgrowth Control

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Solution Overview

Problem

Existing semiconductor devices face challenges in preventing overgrowth of the bottom source/drain region in multi-gate transistors, which can affect the reliability and scalability of integrated circuit devices.

Innovation Solution

The semiconductor device incorporates a specific structure with a lower interlayer insulating layer, insulating patterns, nanosheets, and gate electrodes arranged in a manner that controls the width and spacing of source/drain regions, utilizing insulating materials and etching stop layers to manage the growth of these regions.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If multi-gate transistors with stacked nanosheets are used to increase integration density, then device scaling and current control are improved, but overgrowth of the bottom source/drain region occurs causing reliability issues

Engineering Contradiction:
Improveintegration densityVSAvoiddevice reliability
Core Design Contradiction:
ProductivityVSReliability

Solution Approach 1:

A mandrel structure is introduced as an intermediary element between the bottom source/drain region and the upper nanosheets. The mandrel prevents the bottom source/drain region from overgrowing laterally while still allowing the upper nanosheets to be stacked vertically, thus enabling high integration density without compromising device reliability

Inventive Principle:
Principle #24Intermediary (Mediator)

Solution Approach 2:

The gate structure is segmented into multiple parts: a first gate electrode surrounding the bottom nanosheets, a second gate electrode surrounding the upper nanosheets, and a mandrel structure in between. This segmentation allows independent control of each region, preventing overgrowth while maintaining the multi-gate transistor's current control capability

Inventive Principle:
Principle #1Segmentation

2Manufacturing precision

If the gate electrode width is reduced between adjacent nanosheets to prevent overgrowth, then source/drain region control is improved, but manufacturing precision requirements increase

Engineering Contradiction:
Improvegate width controlVSAvoidgate structure complexity
Core Design Contradiction:
Manufacturing precisionVSDevice complexity

Solution Approach 1:

The gate electrode structure exhibits local quality variations: the first gate electrode has a wider width between adjacent bottom nanosheets to facilitate manufacturing, while the second gate electrode has a narrower width between adjacent upper nanosheets for precise control. This local differentiation allows the system to meet both manufacturing precision and overgrowth prevention requirements

Inventive Principle:
Principle #3Local quality

3Ease of manufacture

If bottom source/drain regions are allowed to grow larger for better electrical contact, then device performance is improved, but overgrowth affects adjacent structures reducing scalability

Engineering Contradiction:
Improvesource/drain contact qualityVSAvoiddevice scalability
Core Design Contradiction:
Ease of manufactureVSAdaptability or versatility

Solution Approach 1:

The invention transitions from two-dimensional lateral growth control to three-dimensional vertical stacking. By stacking upper nanosheets vertically above bottom nanosheets with the mandrel structure in between, the design allows adequate source/drain contact area in the lateral direction while preventing overgrowth from affecting adjacent devices, thus improving both manufacturability and scalability

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

Data Source

PatentUS20260020302A1Semiconductor device
Publication Date: 2026.01.15 SAMSUNG ELECTRONICS CO LTD
  • US20260020302A1 patent drawing
  • US20260020302A1 patent drawing
  • US20260020302A1 patent drawing

AI summary

A semiconductor device includes a lower interlayer insulating layer, an insulating pattern on an upper surface of the lower interlayer insulating layer, a plurality of bottom nanosheets on the insulating pattern, a nanosheet isolation layer on the plurality of bottom nanosheets, the nanosheet isolation layer including an insulating material, a plurality of upper nanosheets on an upper surface of the nanosheet isolation layer, a gate electrode on the insulating pattern, the gate electrode extending around each of the plurality of bottom nanosheets, the nanosheet isolation layer, and the plurality of upper nanosheets, a first bottom source/drain region on a first side of the gate electrode on the insulating pattern, and a first upper source/drain region on the first side of the gate electrode on the first bottom source/drain region, the first upper source/drain region spaced apart from the first bottom source/drain region.